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    SubjectRe: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller
    From
    On 24/11/2022 18:22, Prabhakar wrote:
    > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    >
    > Add DT binding documentation for L2 cache controller found on RZ/Five SoC.
    >
    > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
    > Single) from Andes. The AX45MP core has an L2 cache controller, this patch
    > describes the L2 cache block.
    >
    > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    > ---
    > RFC v3 -> v4
    > * Dropped l2 cache configuration parameters
    > * s/larger/large
    > * Added minItems/maxItems for andestech,pma-regions
    > ---
    > .../cache/andestech,ax45mp-cache.yaml | 93 +++++++++++++++++++
    > .../cache/andestech,ax45mp-cache.h | 38 ++++++++
    > 2 files changed, 131 insertions(+)
    > create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
    > create mode 100644 include/dt-bindings/cache/andestech,ax45mp-cache.h
    >
    > diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
    > new file mode 100644
    > index 000000000000..bf255b177d0a
    > --- /dev/null
    > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
    > @@ -0,0 +1,93 @@
    > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
    > +# Copyright (C) 2022 Renesas Electronics Corp.
    > +%YAML 1.2
    > +---
    > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
    > +$schema: http://devicetree.org/meta-schemas/core.yaml#
    > +
    > +title: Andestech AX45MP L2 Cache Controller
    > +
    > +maintainers:
    > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    > +
    > +description:
    > + A level-2 cache (L2C) is used to improve the system performance by providing
    > + a large amount of cache line entries and reasonable access delays. The L2C
    > + is shared between cores, and a non-inclusive non-exclusive policy is used.
    > +
    > +select:
    > + properties:
    > + compatible:
    > + contains:
    > + enum:
    > + - andestech,ax45mp-cache
    > +
    > + required:
    > + - compatible
    > +
    > +properties:
    > + compatible:
    > + items:
    > + - const: andestech,ax45mp-cache
    > + - const: cache
    > +
    > + reg:
    > + maxItems: 1
    > +
    > + interrupts:
    > + maxItems: 1
    > +
    > + cache-line-size:
    > + const: 64
    > +
    > + cache-level:
    > + const: 2
    > +
    > + cache-sets:
    > + const: 1024
    > +
    > + cache-size:
    > + enum: [131072, 262144, 524288, 1048576, 2097152]
    > +
    > + cache-unified: true
    > +
    > + next-level-cache: true
    > +
    > + andestech,pma-regions:
    > + $ref: /schemas/types.yaml#/definitions/uint32-matrix
    > + minItems: 1
    > + maxItems: 16
    > + items:
    > + minItems: 3
    > + maxItems: 3

    Instead:
    items:
    items:
    - description: Explain
    - description: what is
    - description: here

    > + description: Optional array of memory regions to be set in the PMA.
    > +
    > +additionalProperties: false
    > +
    > +required:
    > + - compatible
    > + - cache-line-size
    > + - cache-level
    > + - cache-sets
    > + - cache-size
    > + - cache-unified
    > + - interrupts
    > + - reg

    Keep the same order as properties appear in the "properties:"

    > +
    > +examples:
    > + - |
    > + #include <dt-bindings/interrupt-controller/irq.h>
    > + #include <dt-bindings/cache/andestech,ax45mp-cache.h>
    > +
    > + cache-controller@2010000 {
    > + reg = <0x13400000 0x100000>;
    > + compatible = "andestech,ax45mp-cache", "cache";
    > + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
    > + cache-line-size = <64>;
    > + cache-level = <2>;
    > + cache-sets = <1024>;
    > + cache-size = <262144>;
    > + cache-unified;
    > + andestech,pma-regions = <0x58000000 0x08000000
    > + (AX45MP_PMACFG_ETYP_NAPOT | AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
    > + };
    > diff --git a/include/dt-bindings/cache/andestech,ax45mp-cache.h b/include/dt-bindings/cache/andestech,ax45mp-cache.h
    > new file mode 100644
    > index 000000000000..aa1cad24075d
    > --- /dev/null
    > +++ b/include/dt-bindings/cache/andestech,ax45mp-cache.h
    > @@ -0,0 +1,38 @@
    > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
    > +/*
    > + * This header provides constants for Andes AX45MP PMA configuration
    > + *
    > + * Copyright (C) 2022 Renesas Electronics Corp.
    > + */
    > +
    > +#ifndef __DT_BINDINGS_ANDESTECH_AX45MP_CACHE_H
    > +#define __DT_BINDINGS_ANDESTECH_AX45MP_CACHE_H
    > +
    > +/* OFF: PMA entry is disabled */
    > +#define AX45MP_PMACFG_ETYP_DISABLED 0
    > +/* Naturally aligned power of 2 region */
    > +#define AX45MP_PMACFG_ETYP_NAPOT 3
    > +
    > +/* Device, Non-bufferable */
    > +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2)
    > +/* Device, bufferable */
    > +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2)
    > +/* Memory, Non-cacheable, Non-bufferable */
    > +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2)
    > +/* Memory, Non-cacheable, Bufferable */
    > +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2)

    What are all these? They don't look like flags, because 3 = 1 | 2...
    they don't look like constants, because we do not use shifts in
    constants. Are these some register values? I also do not see the header
    being used in the code, so why having a bindings header if it is not
    used (DTS is not usage...)?


    > +/* Memory, Write-back, No-allocate */
    > +#define AX45MP_PMACFG_MTYP_MEM_WB_NA (8 << 2)
    > +/* Memory, Write-back, Read-allocate */
    > +#define AX45MP_PMACFG_MTYP_MEM_WB_RA (9 << 2)
    > +/* Memory, Write-back, Write-allocate */
    > +#define AX45MP_PMACFG_MTYP_MEM_WB_WA (10 << 2)
    > +/* Memory, Write-back, Read and Write-allocate */
    > +#define AX45MP_PMACFG_MTYP_MEM_WB_R_WA (11 << 2)
    > +
    > +/* AMO instructions are supported */
    > +#define AX45MP_PMACFG_NAMO_AMO_SUPPORT (0 << 6)
    > +/* AMO instructions are not supported */
    > +#define AX45MP_PMACFG_NAMO_AMO_NO_SUPPORT (1 << 6)
    > +
    > +#endif /* __DT_BINDINGS_ANDESTECH_AX45MP_CACHE_H */

    Best regards,
    Krzysztof

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