Messages in this thread | | | Date | Thu, 24 Nov 2022 21:09:20 +0530 | Subject | Re: [PATCH v2 02/10] arm64: dts: qcom: Add base SM8550 dtsi | From | Sai Prakash Ranjan <> |
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Hi,
On 11/24/2022 7:26 PM, Abel Vesa wrote: > Add base dtsi for SM8550 SoC and includes base description of > CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved > memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, > interconnect, thermal sensor, cpu cooling maps and SMMU nodes > which helps boot to shell with console on boards with this SoC. > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > ---
<snip>...
> + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
This last interrupt must be Hypervisor physical irq(10) and 12 is Hyp virtual irq, so please change it to 10. I guess you got this from downstream but it's not right and they don't boot kernel in EL2.
Thanks, Sai
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