Messages in this thread | | | From | Nathan Barrett-Morrison <> | Subject | RE: [PATCH] spi: cadence-quadspi: Add upper limit safety check to baudrate divisor | Date | Thu, 24 Nov 2022 06:53:54 -0500 |
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Hi Mark & Dhruva,
Your understanding is correct. This is just checking if the divisor field has exceed the bit field's full scale (0xF) in this case. This was observed when we had a reference block of 500MHz and a max SPI clock of 10MHz setting.
500000000/2*10000000 = 25 25 > 0xF (15)
Would you like me to add a dev_err (or such) bailout error condition and resubmit?
Sincerely, Nathan
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