Messages in this thread | | | From | Thomas Gleixner <> | Subject | RE: [patch V2 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support | Date | Thu, 24 Nov 2022 10:10:41 +0100 |
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On Thu, Nov 24 2022 at 03:10, Kevin Tian wrote:
>> From: Thomas Gleixner <tglx@linutronix.de> >> Sent: Monday, November 21, 2022 10:38 PM >> >> The IMS domains have a few constraints: >> >> - The index space is managed by the core code. >> >> Device memory based IMS provides a storage array with a fixed size >> which obviously requires an index. But there is no association between >> index and functionality so the core can randomly allocate an index in >> the array. >> >> Queue memory based IMS does not have the concept of an index as the >> storage is somewhere in memory. In that case the index is purely >> software based to keep track of the allocations. > > 'Queue' could be a HW queue or SW queue. Is it clearer to just use > 'system memory based IMS" here?
Yes
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