Messages in this thread | | | Date | Wed, 23 Nov 2022 11:40:53 +0100 | Subject | Re: [PATCH] ARM: at91: fix build for SAMA5D3 w/o L2 cache | From | Nicolas Ferre <> |
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On 23/11/2022 at 09:38, Peter Rosin wrote: > Hi! > > 2022-11-23 at 08:19, Claudiu.Beznea@microchip.com wrote: >> On 22.11.2022 19:14, Clément Léger wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> Le Tue, 22 Nov 2022 16:13:40 +0100, >>> Thorsten Leemhuis <regressions@leemhuis.info> a écrit : >>> >>>> Hi, this is your Linux kernel regression tracker. >>>> >>>> On 12.11.22 16:40, Peter Rosin wrote: >>>>> The L2 cache is present on the newer SAMA5D2 and SAMA5D4 families, but >>>>> apparently not for the older SAMA5D3. At least not always. >> >> Peter, what do you mean by "at least not always" here? Are you talking >> about the OUTER_CACHE flag? > > I'm not familiar with all options for L2 caching. I was just being cautious > to not exclude the possibility that there could be some variation within > the SAMA5D3 series (I'm on SAMA5D31) or with an external L2 cache or > something such. If there's simply no possible way to have an L2 cache on > any SAMA5D3, feel free to edit that "At least not always" out while you > commit.
I confirm that there is no L2 cache in any variant of SAMA5D3.
[..]
Thanks, best regards, Nicolas -- Nicolas Ferre
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