Messages in this thread | | | Date | Tue, 22 Nov 2022 11:10:16 +0200 | From | Andy Shevchenko <> | Subject | Re: [PATCH v3 1/4] x86/of: Convert Intel's APIC bindings to YAML schema |
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On Tue, Nov 22, 2022 at 03:39:07PM +0800, Rahul Tanwar wrote: > Intel's APIC family of interrupt controllers support local APIC > (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic > & ioapic from text to YAML schema. Separate lapic & ioapic schemas. > Addditionally, add description which was missing in text file and > add few more required standard properties which were also missing > in text file.
...
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
> +maintainers: > + - Sebastian Andrzej Siewior <bigeasy@linutronix.de>
I'm not sure, you need to have a confirmation before putting someone's name here. Yours is easier to add.
> +description: | > + Intel's Advanced Programmable Interrupt Controller (APIC) is a > + family of interrupt controllers. The APIC is a split > + architecture design, with a local component (LAPIC) integrated > + into the processor itself and an external I/O APIC. Local APIC > + (lapic) receives interrupts from the processor's interrupt pins, > + from internal sources and from an external I/O APIC (ioapic). > + And it sends these to the processor core for handling.
> + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
Dunno if schema has special format for data sheet links...
> + Chapter 8 for more details. > + > + Many of the Intel's generic devices like hpet, ioapic, lapic have > + the ce4100 name in their compatible property names because they
> + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more
Shouldn't you change this?
> + details on it. > + > + This schema defines bindings for I/O APIC interrupt controller.
...
> +maintainers: > + - Sebastian Andrzej Siewior <bigeasy@linutronix.de> > + > + > +description: | > + Intel's Advanced Programmable Interrupt Controller (APIC) is a > + family of interrupt controllers. The APIC is a split > + architecture design, with a local component (LAPIC) integrated > + into the processor itself and an external I/O APIC. Local APIC > + (lapic) receives interrupts from the processor's interrupt pins, > + from internal sources and from an external I/O APIC (ioapic). > + And it sends these to the processor core for handling. > + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf > + Chapter 8 for more details. > + > + Many of the Intel's generic devices like hpet, ioapic, lapic have > + the ce4100 name in their compatible property names because they > + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more > + details on it. > + > + This schema defines bindings for local APIC interrupt controller.
Same two comments as per above.
-- With Best Regards, Andy Shevchenko
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