Messages in this thread | | | From | Tudor Ambarus <> | Subject | Re: [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a | Date | Mon, 21 Nov 2022 17:11:22 +0200 |
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On Thu, 20 Oct 2022 09:20:58 +0000, Eliav Farber wrote: > mt25qu256a [1] uses the 4 bit Block Protection scheme and supports > Top/Bottom protection via the BP and TB bits of the Status Register. > BP3 is located in bit 6 of the Status Register. > Tested on MT25QU256ABA8ESF-0SIT. > > [1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf > > [...]
Applied to spi-nor/next, thanks!
[1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a https://git.kernel.org/mtd/c/bcc0c61e6134
Best regards, -- Tudor Ambarus <tudor.ambarus@microchip.com>
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