lkml.org 
[lkml]   [2022]   [Nov]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH v3 3/5] arm64: dts: mediatek: asurada: Enable internal display
Date
The asurada platform has an ANX7625 bridge connecting the DSI's output
to the internal eDP panel. Add and enable these devices in order to get
a usable internal display.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---

(no changes since v1)

.../boot/dts/mediatek/mt8192-asurada.dtsi | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index 666021ca4d4f..ace44827de17 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -198,6 +198,14 @@ wifi_restricted_dma_region: wifi@c0000000 {
};
};

+&dsi0 {
+ status = "okay";
+};
+
+&dsi_out {
+ remote-endpoint = <&anx7625_in>;
+};
+
&i2c0 {
status = "okay";

@@ -246,6 +254,53 @@ &i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
+
+ anx_bridge: anx7625@58 {
+ compatible = "analogix,anx7625";
+ reg = <0x58>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&anx7625_pins>;
+ enable-gpios = <&pio 41 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
+ vdd10-supply = <&pp1000_mipibrdg>;
+ vdd18-supply = <&pp1800_mipibrdg>;
+ vdd33-supply = <&pp3300_mipibrdg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ anx7625_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ anx7625_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ aux-bus {
+ panel: panel {
+ compatible = "edp-panel";
+ power-supply = <&pp3300_mipibrdg>;
+ backlight = <&backlight_lcd0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&anx7625_out>;
+ };
+ };
+ };
+ };
+ };
};

&i2c7 {
@@ -256,6 +311,10 @@ &i2c7 {
pinctrl-0 = <&i2c7_pins>;
};

+&mipi_tx0 {
+ status = "okay";
+};
+
&mmc0 {
status = "okay";

@@ -587,6 +646,20 @@ &pio {
"AUD_DAT_MISO0",
"AUD_DAT_MISO1";

+ anx7625_pins: anx7625-default-pins {
+ pins-out {
+ pinmux = <PINMUX_GPIO41__FUNC_GPIO41>,
+ <PINMUX_GPIO42__FUNC_GPIO42>;
+ output-low;
+ };
+
+ pins-in {
+ pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
cr50_int: cr50-irq-default-pins {
pins-gsc-ap-int-odl {
pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
--
2.38.1
\
 
 \ /
  Last update: 2022-11-02 20:09    [W:0.241 / U:0.444 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site