lkml.org 
[lkml]   [2022]   [Nov]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH 9/9] arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock names
Date
Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix
IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC
driver is relying on the old names to match them as they are being used as
the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.

This broke parenting as GCC could not find the parent clock, so fix it by
changing to the names that driver is expecting.

Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index c76c6ee9acb6..6f5d447c9ee7 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -257,7 +257,7 @@ pcie_phy0: phy@84200 {
#clock-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "pcie_0_pipe_clk";
+ clock-output-names = "pcie20_phy0_pipe_clk";
};
};

@@ -285,7 +285,7 @@ pcie_phy1: phy@8e200 {
#clock-cells = <0>;
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "pcie_1_pipe_clk";
+ clock-output-names = "pcie20_phy1_pipe_clk";
};
};

--
2.38.1
\
 
 \ /
  Last update: 2022-11-16 22:51    [W:0.114 / U:0.588 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site