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SubjectRE: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put the PM clocks
Date
> Subject: RE: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put
> the PM clocks
>
>
>
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: 14 November 2022 19:04
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Prabhakar <prabhakar.csengg@gmail.com>; Geert Uytterhoeven
> > <geert+renesas@glider.be>; Wim Van Sebroeck <wim@linux-
> watchdog.org>;
> > Guenter Roeck <linux@roeck-us.net>; Philipp Zabel
> > <p.zabel@pengutronix.de>; linux- watchdog@vger.kernel.org;
> > linux-kernel@vger.kernel.org; linux-renesas- soc@vger.kernel.org;
> > Fabrizio Castro <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev
> > Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: Re: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we
> put
> > the PM clocks
> >
> > Hi Biju,
> >
> > On Mon, Nov 14, 2022 at 7:42 PM Biju Das
> <biju.das.jz@bp.renesas.com> wrote:
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: 14 November 2022 18:09
> > > > To: Geert Uytterhoeven <geert+renesas@glider.be>; Wim Van
> Sebroeck
> > > > <wim@linux-watchdog.org>; Guenter Roeck <linux@roeck-us.net>;
> > > > Philipp Zabel <p.zabel@pengutronix.de>;
> > > > linux-watchdog@vger.kernel.org
> > > > Cc: linux-kernel@vger.kernel.org;
> > > > linux-renesas-soc@vger.kernel.org;
> > > > Prabhakar <prabhakar.csengg@gmail.com>; Biju Das
> > > > <biju.das.jz@bp.renesas.com>; Fabrizio Castro
> > > > <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev- lad.rj@bp.renesas.com>
> > > > Subject: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we
> put
> > > > the PM clocks
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > On RZ/Five SoC it was observed that setting timeout (to say 1
> sec)
> > > > wouldn't reset the system. To fix this we make sure we issue a
> > > > reset before putting the PM clocks to make sure the registers
> have
> > > > been
> > cleared.
> > > >
> > > > While at it re-used rzg2l_wdt_stop() in rzg2l_wdt_set_timeout()
> as
> > > > we were calling the same functions here.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > Note,
> > > > - This patch has been tested on RZ/G2L, RZ/V2M and RZ/Five.
> > > > - My initial investigation showed adding the delay after
> > > > pm_runtime_get_sync()
> > > > also fixed this issue.
> > > > - Do I need add the fixes tag ? what should be the operation
> PUT-
> > > > >RESET/RESET->PUT?
> > >
> > > It looks like timing issue, None of the previous devices are
> > > affected by
> > this.
> >
> > To me it looks like the device must be clocked for the reset signal
> to
> > be propagated?
>
> Yep, provide clk supply for a device, then apply reset.

Maybe we need to make it consistent by taking care of [1]

Current patch: CLK ON -> apply Reset for V2M.
[1]: Apply Reset -> CLK ON for V2M.

[1] https://lore.kernel.org/linux-renesas-soc/CAMuHMdUWbT6VArm9B56VE0yUYWCTm=3vMGrrONSv9cdsQQnhpg@mail.gmail.com/T/#mdb78503524a8f4207f59a40f7ff573e210656988

Cheers,
Biju
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