Messages in this thread | | | Date | Tue, 15 Nov 2022 17:54:13 +0100 | From | Marc Kleine-Budde <> | Subject | Re: [PATCH v2] spi: spi-imx: Fix spi_bus_clk if requested clock is higher than input clock |
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On 15.11.2022 17:26:53, Frieder Schrempf wrote: > From: Frieder Schrempf <frieder.schrempf@kontron.de> > > In case the requested bus clock is higher than the input clock, the correct > dividers (pre = 0, post = 0) are returned from mx51_ecspi_clkdiv(), but > *fres is left uninitialized and therefore contains an arbitrary value. > > This causes trouble for the recently introduced PIO polling feature as the > value in spi_imx->spi_bus_clk is used there to calculate for which > transfers to enable PIO polling. > > Fix this by setting *fres even if no clock dividers are in use. > > This issue was observed on Kontron BL i.MX8MM with an SPI peripheral clock set > to 50 MHz by default and a requested SPI bus clock of 80 MHz for the SPI NOR > flash. > > With the fix applied the debug message from mx51_ecspi_clkdiv() now prints the > following: > > spi_imx 30820000.spi: mx51_ecspi_clkdiv: fin: 50000000, fspi: 50000000, > post: 0, pre: 0 > > Fixes: 07e759387788 ("spi: spi-imx: add PIO polling support")
The *fres parameter was introduced in:
| Fixes: 6fd8b8503a0d ("spi: spi-imx: Fix out-of-order CS/SCLK operation at low speeds")
The exiting code:
| if (unlikely(fspi > fin)) | return 0;
was not sufficient any more and should be fixed.
Marc
-- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung West/Dortmund | Phone: +49-231-2826-924 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | [unhandled content-type:application/pgp-signature] | |