Messages in this thread | | | From | Rahul Tanwar <> | Subject | Re: [PATCH RESEND 1/1] x86/of: Add support for boot time interrupt mode config | Date | Mon, 14 Nov 2022 10:00:02 +0000 |
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Hi Andy,
Thanks for response.
On 14/11/2022 5:45 pm, Andy Shevchenko wrote: > This email was sent from outside of MaxLinear. > > > On Mon, Nov 14, 2022 at 05:20:06PM +0800, Rahul Tanwar wrote: >> Presently, init/boot time interrupt delivery mode is enumerated only >> for ACPI enabled systems by parsing MADT table or for older systems >> by parsing MP table. But for OF based x86 systems, it is assumed & >> fixed to legacy PIC mode. >> >> Add support for configuration of init time interrupt delivery mode for >> x86 OF based systems by introducing a new optional boolean property >> 'intel,no-imcr' for interrupt-controller node of local APIC. This >> property emulates IMCRP Bit 7 of MP feature info byte 2 of MP >> floating pointer structure. >> >> Defaults to legacy PIC mode if absent. Configures it to virtual wire >> compatibility mode if present. > > ... > >> + if (of_property_read_bool(dn, "intel,no-imcr")) { > > I can't find this property in the Documentation/devicetree/bindings. > > Moreover, I prefer to see positive one, something like: > > intel,virtual-wire-bla-bla-bla > > Please consult with DT people on how properly name it.
Yes, agree. Need to add it in bindings doc after finalizing the property name. I chose "intel,no-imcr" to have a direct correlation with the MPS spec defined data field for the same purpose. It reads below bit in mpparse code to detect PIC mode or virtual wire mode.
Bit 7: IMCRP. When the IMCR presence bit is set, the IMCR is present and PIC Mode is implemented; otherwise, Virtual Wire Mode is implemented.
Please refer [1]
[1] https://www.manualslib.com/manual/77733/Intel Multiprocessor.html?page=40#manual
Regards, Rahul
> >> + pr_info(" Virtual Wire compatibility mode.\n"); >> + pic_mode = 0; >> + } else { >> + pr_info(" IMCR and PIC compatibility mode.\n"); >> + pic_mode = 1; >> + } > > -- > With Best Regards, > Andy Shevchenko > > >
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