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    SubjectRe: [PATCH 6/9] dt-bindings: Add RISC-V advanced PLIC bindings
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    On 11/11/2022 05:42, Anup Patel wrote:
    > We add DT bindings document for RISC-V advanced platform level interrupt
    > controller (APLIC) defined by the RISC-V advanced interrupt architecture
    > (AIA) specification.
    >
    > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
    > ---
    > .../interrupt-controller/riscv,aplic.yaml | 136 ++++++++++++++++++
    > 1 file changed, 136 insertions(+)
    > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
    >
    > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
    > new file mode 100644
    > index 000000000000..0aa48571f3bc
    > --- /dev/null
    > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
    > @@ -0,0 +1,136 @@
    > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    > +%YAML 1.2
    > +---
    > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
    > +$schema: http://devicetree.org/meta-schemas/core.yaml#
    > +
    > +title: RISC-V Advancded Platform Level Interrupt Controller (APLIC)
    > +
    > +maintainers:
    > + - Anup Patel <anup@brainfault.org>
    > +
    > +description:
    > + The RISC-V advanced interrupt architecture (AIA) defines advanced platform
    > + level interrupt controller (APLIC) for handling wired interrupts in a
    > + RISC-V platform. The RISC-V AIA specification can be found at
    > + https://github.com/riscv/riscv-aia.
    > +
    > + The RISC-V APLIC is implemented as hierarchical APLIC domains where all
    > + interrupt sources connect to the root domain which can further delegate
    > + interrupts to child domains. We have one device tree node for each APLIC
    > + domain.
    > +
    > +allOf:
    > + - $ref: /schemas/interrupt-controller.yaml#
    > +
    > +properties:
    > + compatible:
    > + items:
    > + - enum:
    > + - vendor,chip-aplic
    > + - const: riscv,aplic
    > +
    > + reg:
    > + maxItems: 1
    > +
    > + interrupt-controller: true
    > +
    > + "#interrupt-cells":
    > + const: 2
    > +
    > + interrupts-extended:
    > + minItems: 1
    > + maxItems: 16384
    > + description:
    > + The presence of this property implies that given APLIC domain directly
    > + injects external interrupts to a set of RISC-V HARTS (or CPUs). Each
    > + node pointed to should be a riscv,cpu-intc node, which has a riscv node
    > + (i.e. RISC-V HART) as parent.
    > +
    > + msi-parent:
    > + description:
    > + The presence of this property implies that given APLIC domain forwards

    Drop "The presence of this property" and make it a proper sentence
    describing hardware.

    > + wired interrupts as MSIs to a AIA incoming message signaled interrupt
    > + controller (IMSIC). This property should be considered only when the
    > + interrupts-extended property is absent.
    > +
    > + riscv,num-sources:
    > + $ref: "/schemas/types.yaml#/definitions/uint32"

    Drop quotes.

    > + minimum: 1
    > + maximum: 1023
    > + description:
    > + Specifies how many wired interrupts are supported by this APLIC domain.
    > +
    > + riscv,children:
    > + $ref: '/schemas/types.yaml#/definitions/phandle-array'
    > + minItems: 1
    > + maxItems: 1024
    > + description:
    > + This property represents a list of child APLIC domains for the given
    > + APLIC domain. Each child APLIC domain is assigned child index in
    > + increasing order with the first child APLIC domain assigned child
    > + index 0. The APLIC domain child index is used by firmware to delegate
    > + interrupts from the given APLIC domain to a particular child APLIC
    > + domain.
    > +
    > + riscv,delegate:
    > + $ref: '/schemas/types.yaml#/definitions/phandle-array'
    > + minItems: 1
    > + maxItems: 1024
    > + description:
    > + This property represents a interrupt delegation list where each entry

    Drop "This property represents".

    > + is a triple consisting of child APLIC domain phandle, first interrupt
    > + number, and last interrupt number. The firmware will configure interrupt
    > + delegation registers based on interrupt delegation list.
    > +
    > +additionalProperties: false

    Same comments as in previous patch,

    > +
    > +required:
    > + - compatible
    > + - reg
    > + - interrupt-controller
    > + - "#interrupt-cells"
    > + - riscv,num-sources
    > +
    > +examples:
    > + - |
    > + // Example 1 (APIC domain directly injecting interrupt to HARTs):
    > +
    > + aplic0: interrupt-controller@c000000 {
    > + compatible = "vendor,chip-aplic", "riscv,aplic";
    > + interrupts-extended = <&cpu1_intc 11>,
    > + <&cpu2_intc 11>,
    > + <&cpu3_intc 11>,
    > + <&cpu4_intc 11>;
    > + reg = <0xc000000 0x4080>;
    > + interrupt-controller;
    > + #interrupt-cells = <2>;
    > + riscv,num-sources = <63>;
    > + riscv,children = <&aplic1>;
    > + riscv,delegate = <&aplic1 1 63>;
    > + };
    > +
    > + aplic1: interrupt-controller@d000000 {
    > + compatible = "vendor,chip-aplic", "riscv,aplic";
    > + interrupts-extended = <&cpu1_intc 9>,
    > + <&cpu2_intc 9>,
    > + <&cpu3_intc 9>,
    > + <&cpu4_intc 9>;
    > + reg = <0xd000000 0x4080>;
    > + interrupt-controller;
    > + #interrupt-cells = <2>;
    > + riscv,num-sources = <63>;
    > + };
    > +
    > + - |
    > + // Example 2 (APIC domain forwarding interrupts as MSIs):
    > +
    > + interrupt-controller@d000000 {
    > + compatible = "vendor,chip-aplic", "riscv,aplic";
    > + msi-parent = <&imsics>;
    > + reg = <0xd000000 0x4000>;
    > + interrupt-controller;
    > + #interrupt-cells = <2>;
    > + riscv,num-sources = <63>;

    It's almost the same as previous... don't add unnecessary examples
    (difference in one property usually does not mean you need new example).

    > + };
    > +...

    Best regards,
    Krzysztof

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