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    SubjectRe: [PATCH v4 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485 support to quad-uart driver
    On Fri, Nov 11, 2022 at 09:41:29PM +0530, Kumaravel Thiagarajan wrote:
    > pci1xxxx uart supports rs485 mode of operation in the hardware with

    UART
    RS485 (same in the subject)

    > auto-direction control with configurable delay for releasing RTS after
    > the transmission. This patch adds support for the rs485 mode.

    RS485

    ...

    > Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
    > Signed-off-by: Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>

    No Co-developed-by?

    ...

    > +static int pci1xxxx_rs485_config(struct uart_port *port,
    > + struct ktermios *termios,
    > + struct serial_rs485 *rs485)
    > +{
    > + u32 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);

    > + u8 delay_in_baud_periods = 0;
    > + u32 baud_period_in_ns = 0;

    Why these assignments?

    > + u32 data = 0;
    > +
    > + /* pci1xxxx's uart hardware supports only RTS delay after
    > + * Tx and in units of bit times to a maximum of 15
    > + */

    /*
    * Use proper multi-line
    * comment style.
    */

    > + if (rs485->flags & SER_RS485_ENABLED) {
    > + data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;
    > +
    > + if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
    > + data |= ADCL_CFG_POL_SEL;
    > +
    > + if (rs485->delay_rts_after_send) {
    > + baud_period_in_ns =
    > + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) *
    > + UART_BIT_SAMPLE_CNT;
    > + delay_in_baud_periods =
    > + (rs485->delay_rts_after_send * NSEC_PER_MSEC) /
    > + baud_period_in_ns;
    > + delay_in_baud_periods =
    > + min_t(u8, delay_in_baud_periods,
    > + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));
    > + data |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK,
    > + delay_in_baud_periods);
    > + rs485->delay_rts_after_send =
    > + (baud_period_in_ns * delay_in_baud_periods) /
    > + NSEC_PER_MSEC;
    > + rs485->delay_rts_before_send = 0;
    > + }
    > + }
    > + writel(data, port->membase + ADCL_CFG_REG);
    > + return 0;
    > +}

    --
    With Best Regards,
    Andy Shevchenko


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