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    SubjectRe: [PATCH 2/7] hte: Add Tegra234 provider
    On Thu, Nov 03, 2022 at 10:45:18AM -0700, Dipen Patel wrote:
    > The Tegra234 AON GPIO instance and LIC IRQ support HTE. For the GPIO
    > HTE support, it requires to add mapping between GPIO and HTE framework.
    >
    > Signed-off-by: Dipen Patel <dipenp@nvidia.com>
    > ---
    > drivers/hte/hte-tegra194-test.c | 2 +-
    > drivers/hte/hte-tegra194.c | 124 ++++++++++++++++++++++++++++++--
    > 2 files changed, 121 insertions(+), 5 deletions(-)
    >
    > diff --git a/drivers/hte/hte-tegra194-test.c b/drivers/hte/hte-tegra194-test.c
    > index 5d776a185bd6..d79c28a80517 100644
    > --- a/drivers/hte/hte-tegra194-test.c
    > +++ b/drivers/hte/hte-tegra194-test.c
    > @@ -16,7 +16,7 @@
    > #include <linux/hte.h>
    >
    > /*
    > - * This sample HTE GPIO test driver demonstrates HTE API usage by enabling
    > + * This sample HTE test driver demonstrates HTE API usage by enabling
    > * hardware timestamp on gpio_in and specified LIC IRQ lines.
    > *
    > * Note: gpio_out and gpio_in need to be shorted externally in order for this
    > diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c
    > index 49a27af22742..5d1f947db0f6 100644
    > --- a/drivers/hte/hte-tegra194.c
    > +++ b/drivers/hte/hte-tegra194.c
    > @@ -62,6 +62,10 @@
    > #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25
    > #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26
    > #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27
    > +#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28
    > +#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29
    > +#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30
    > +#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31
    >
    > #define HTE_TECTRL 0x0
    > #define HTE_TETSCH 0x4
    > @@ -220,7 +224,100 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = {
    > [39] = {NV_AON_SLICE_INVALID, 0},
    > };
    >
    > -static const struct tegra_hte_data aon_hte = {
    > +static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = {
    > + /* gpio, slice, bit_index */
    > + /* AA port */
    > + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
    > + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
    > + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
    > + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
    > + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
    > + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
    > + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
    > + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
    > + /* BB port */
    > + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
    > + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
    > + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
    > + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
    > + /* CC port */
    > + [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
    > + [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
    > + [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
    > + [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
    > + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
    > + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
    > + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
    > + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
    > + /* DD port */
    > + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
    > + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
    > + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
    > + /* EE port */
    > + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
    > + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
    > + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
    > + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
    > + [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
    > + [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
    > + [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
    > + [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
    > + /* GG port */
    > + [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
    > +};
    > +
    > +static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {
    > + /* gpio, slice, bit_index */
    > + /* AA port */
    > + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
    > + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
    > + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
    > + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
    > + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
    > + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
    > + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
    > + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
    > + /* BB port */
    > + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
    > + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
    > + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
    > + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
    > + [12] = {NV_AON_SLICE_INVALID, 0},
    > + [13] = {NV_AON_SLICE_INVALID, 0},
    > + [14] = {NV_AON_SLICE_INVALID, 0},
    > + [15] = {NV_AON_SLICE_INVALID, 0},
    > + /* CC port */
    > + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
    > + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
    > + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
    > + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
    > + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
    > + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
    > + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
    > + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
    > + /* DD port */
    > + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
    > + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
    > + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
    > + [27] = {NV_AON_SLICE_INVALID, 0},
    > + [28] = {NV_AON_SLICE_INVALID, 0},
    > + [29] = {NV_AON_SLICE_INVALID, 0},
    > + [30] = {NV_AON_SLICE_INVALID, 0},
    > + [31] = {NV_AON_SLICE_INVALID, 0},
    > + /* EE port */
    > + [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
    > + [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
    > + [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
    > + [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
    > + [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
    > + [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
    > + [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
    > + [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
    > + /* GG port */
    > + [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
    > +};
    > +
    > +static const struct tegra_hte_data t194_aon_hte = {
    > .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
    > .map = tegra194_aon_gpio_map,
    > .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
    > @@ -228,6 +325,14 @@ static const struct tegra_hte_data aon_hte = {
    > .type = HTE_TEGRA_TYPE_GPIO,
    > };
    >
    > +static const struct tegra_hte_data t234_aon_hte = {
    > + .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map),
    > + .map = tegra234_aon_gpio_map,
    > + .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map),
    > + .sec_map = tegra234_aon_gpio_sec_map,
    > + .type = HTE_TEGRA_TYPE_GPIO,
    > +};
    > +
    > static const struct tegra_hte_data lic_hte = {
    > .map_sz = 0,
    > .map = NULL,
    > @@ -535,7 +640,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip,
    >
    > static const struct of_device_id tegra_hte_of_match[] = {
    > { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
    > - { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte},
    > + { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
    > + { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte},
    > + { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
    > { }
    > };
    > MODULE_DEVICE_TABLE(of, tegra_hte_of_match);
    > @@ -635,8 +742,17 @@ static int tegra_hte_probe(struct platform_device *pdev)
    >
    > gc->match_from_linedata = tegra_hte_match_from_linedata;
    >
    > - hte_dev->c = gpiochip_find("tegra194-gpio-aon",
    > - tegra_get_gpiochip_from_name);
    > + if (of_device_is_compatible(dev->of_node,
    > + "nvidia,tegra194-gte-aon"))
    > + hte_dev->c = gpiochip_find("tegra194-gpio-aon",
    > + tegra_get_gpiochip_from_name);
    > + else if (of_device_is_compatible(dev->of_node,
    > + "nvidia,tegra234-gte-aon"))
    > + hte_dev->c = gpiochip_find("tegra234-gpio-aon",
    > + tegra_get_gpiochip_from_name);
    > + else
    > + return -ENODEV;

    I'm wondering: instead of doing this cumbersome lookup, perhaps it would
    be easier to create a direct link to the right GPIO controller with a
    phandle?

    Thierry
    [unhandled content-type:application/pgp-signature]
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