Messages in this thread | | | From | Sherry Sun <> | Subject | RE: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to support wifi | Date | Fri, 11 Nov 2022 09:18:52 +0000 |
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> -----Original Message----- > From: Peng Fan <peng.fan@nxp.com> > Sent: 2022年11月11日 17:08 > To: Marco Felsch <m.felsch@pengutronix.de>; Peng Fan (OSS) > <peng.fan@oss.nxp.com> > Cc: shawnguo@kernel.org; s.hauer@pengutronix.de; linux- > kernel@vger.kernel.org; Sherry Sun <sherry.sun@nxp.com>; > kernel@pengutronix.de; festevam@gmail.com; linux-arm- > kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com> > Subject: RE: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to > support wifi > > Sherry, > > > Subject: Re: [PATCH V4 12/14] arm64: dts: imx8mm-evk: Enable usdhc1 to > > support wifi > > > > Hi Peng, > > > > On 22-11-11, Peng Fan (OSS) wrote: > > > From: Sherry Sun <sherry.sun@nxp.com> > > > > > > Enable usdhc1 which is used for wifi. > > > > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > > --- > > > arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 27 +++++++++++++ > > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39 > > +++++++++++++++++++ > > > 2 files changed, 66 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > > > index a2b24d4d4e3e..7b80f144327d 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts > > > @@ -15,6 +15,13 @@ / { > > > aliases { > > > spi0 = &flexspi; > > > }; > > > + > > > + usdhc1_pwrseq: usdhc1_pwrseq { > > > + compatible = "mmc-pwrseq-simple"; > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&pinctrl_usdhc1_gpio>; > > > + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; > > > + }; > > > }; > > > > > > &ddrc { > > > @@ -53,6 +60,19 @@ flash@0 { > > > }; > > > }; > > > > > > +&usdhc1 { > > > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > > > + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; > > > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; > > > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; > > > + bus-width = <4>; > > > + keep-power-in-suspend; > > > + mmc-pwrseq = <&usdhc1_pwrseq>; > > > + non-removable; > > > + wakeup-source; > > > + status = "okay"; > > > +}; > > > + > > > &usdhc3 { > > > assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; > > > assigned-clock-rates = <400000000>; @@ -125,4 +145,11 @@ > > > MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 > > 0x1d6 > > > MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE > > 0x196 > > > >; > > > }; > > > + > > > + pinctrl_wlan: wlangrp { > > > + fsl,pins = < > > > + > > MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K > > 0x141 > > > + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 > > 0x159 > > > + >; > > > + }; > > > > Out of curiousity, this is not shareable with the other ddr4 evk? > [Peng Fan] > > Could you please help answer? >
Hi Peng, I suggest to remove the pinctrl_wlan configure here, it should be added along with the wifi wowlan subnode later.
Best Regards Sherry
> Thanks, > Peng. > > > > > Regards, > > Marco > > > > > }; > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > index 7d6317d95b13..ce450965e837 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi > > > @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX > > 0x140 > > > >; > > > }; > > > > > > + pinctrl_usdhc1_gpio: usdhc1grpgpio { > > > + fsl,pins = < > > > + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 > > > + >; > > > + }; > > > + > > > + pinctrl_usdhc1: usdhc1grp { > > > + fsl,pins = < > > > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > > 0x190 > > > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > > 0x1d0 > > > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > > 0x1d0 > > > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > > 0x1d0 > > > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > > 0x1d0 > > > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > > 0x1d0 > > > + >; > > > + }; > > > + > > > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > > > + fsl,pins = < > > > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > > 0x194 > > > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > > 0x1d4 > > > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > > 0x1d4 > > > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > > 0x1d4 > > > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > > 0x1d4 > > > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > > 0x1d4 > > > + >; > > > + }; > > > + > > > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > > > + fsl,pins = < > > > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > > 0x196 > > > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > > 0x1d6 > > > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > > 0x1d6 > > > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > > 0x1d6 > > > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > > 0x1d6 > > > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > > 0x1d6 > > > + >; > > > + }; > > > + > > > pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { > > > fsl,pins = < > > > MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 > > 0x1c4 > > > -- > > > 2.37.1 > > > > > > > > >
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