Messages in this thread | | | From | Heiko Stübner <> | Subject | Re: [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm | Date | Fri, 07 Oct 2022 11:22:09 +0200 |
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Am Donnerstag, 6. Oktober 2022, 09:08:13 CEST schrieb Jisheng Zhang: > We will make use of ISA extension in asm files, so make the multi-letter > RISC-V ISA extension IDs macros rather than enums and move them and > those base ISA extension IDs to suitable place. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/include/asm/hwcap.h | 45 +++++++++++++++++----------------- > 1 file changed, 23 insertions(+), 22 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 6f59ec64175e..6cf445653911 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -12,20 +12,6 @@ > #include <linux/bits.h> > #include <uapi/asm/hwcap.h> > > -#ifndef __ASSEMBLY__ > -#include <linux/jump_label.h> > -/* > - * This yields a mask that user programs can use to figure out what > - * instruction set this cpu supports. > - */ > -#define ELF_HWCAP (elf_hwcap) > - > -enum { > - CAP_HWCAP = 1, > -}; > - > -extern unsigned long elf_hwcap; > - > #define RISCV_ISA_EXT_a ('a' - 'a') > #define RISCV_ISA_EXT_c ('c' - 'a') > #define RISCV_ISA_EXT_d ('d' - 'a') > @@ -46,21 +32,36 @@ extern unsigned long elf_hwcap; > #define RISCV_ISA_EXT_BASE 26 > > /* > - * This enum represent the logical ID for each multi-letter RISC-V ISA extension. > + * These macros represent the logical ID for each multi-letter RISC-V ISA extension. > * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed > * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter > * extensions while all the multi-letter extensions should define the next > * available logical extension id. > */ > -enum riscv_isa_ext_id { > - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > - RISCV_ISA_EXT_SVPBMT, > - RISCV_ISA_EXT_ZICBOM, > - RISCV_ISA_EXT_ZIHINTPAUSE, > - RISCV_ISA_EXT_SSTC, > - RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > +#define RISCV_ISA_EXT_SSCOFPMF 26 > +#define RISCV_ISA_EXT_SVPBMT 27 > +#define RISCV_ISA_EXT_ZICBOM 28 > +#define RISCV_ISA_EXT_ZIHINTPAUSE 29 > +#define RISCV_ISA_EXT_SSTC 30 > + > +#define RISCV_ISA_EXT_ID_MAX RISCV_ISA_EXT_MAX > + > +
nit: double empty line
> +#ifndef __ASSEMBLY__ > +#include <linux/jump_label.h> > +/* > + * This yields a mask that user programs can use to figure out what > + * instruction set this cpu supports. > + */ > +#define ELF_HWCAP (elf_hwcap) > + > +enum { > + CAP_HWCAP = 1, > }; > > +extern unsigned long elf_hwcap; > + > +
nit: double empty line, otherwise
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> /* > * This enum represents the logical ID for each RISC-V ISA extension static > * keys. We can use static key to optimize code path if some ISA extensions >
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