Messages in this thread | | | Date | Thu, 6 Oct 2022 18:54:31 -0700 | From | Pawan Gupta <> | Subject | Re: [PATCH] x86/speculation: Mitigate eIBRS PBRSB predictions with WRMSR |
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Hi Suraj,
On Wed, Oct 05, 2022 at 03:02:27PM -0700, Suraj Jitindar Singh wrote: >tl;dr: The existing mitigation for eIBRS PBRSB predictions uses an INT3 to >ensure a call instruction retires before a following unbalanced RET. Replace >this with a WRMSR serialising instruction which has a lower performance >penalty. > >== Background == > >eIBRS (enhanced indirect branch restricted speculation) is used to prevent >predictor addresses from one privilege domain from being used for prediction >in a higher privilege domain. > >== Problem == > >On processors with eIBRS protections there can be a case where upon VM exit >a guest address may be used as an RSB prediction for an unbalanced RET if a >CALL instruction hasn't yet been retired. This is termed PBRSB (Post-Barrier >Return Stack Buffer). > >A mitigation for this was introduced in: >(2b1299322016731d56807aa49254a5ea3080b6b3 x86/speculation: Add RSB VM Exit protections) > >This mitigation [1] has a ~1% performance impact on VM exit compared to without >it [2]. > >== Solution == > >The WRMSR instruction can be used as a speculation barrier and a serialising >instruction. Use this on the VM exit path instead to ensure that a CALL >instruction (in this case the call to vmx_spec_ctrl_restore_host) has retired >before the prediction of a following unbalanced RET. > >This mitigation [3] has a negligible performance impact. > >== Testing == > >Run the outl_to_kernel kvm-unit-tests test 200 times per configuration which >counts the cycles for an exit to kernel mode. > >[1] With existing mitigation: >Average: 2026 cycles >[2] With no mitigation: >Average: 2008 cycles
During these tests was the value of MSR SPEC_CTRL for host and guest different?
>[3] With proposed mitigation: >Average: 2008 cycles
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