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    Subject[PATCH v2 04/15] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC
    Date
    UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
    required register settings using the tables_hs_g4 struct instance. This
    also requires a separate qmp_phy_cfg for SM8250 instead of SM8150.

    Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    ---
    drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 68 ++++++++++++++++++++++++-
    1 file changed, 67 insertions(+), 1 deletion(-)

    diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
    index 5f2a012707b7..fa7457c0202b 100644
    --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
    +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
    @@ -385,6 +385,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
    QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
    };

    +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
    +};
    +
    static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
    QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
    QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
    @@ -420,7 +424,32 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
    QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
    QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
    QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
    +};

    +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
    + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
    };

    static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
    @@ -433,6 +462,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
    QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
    };

    +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_pcs[] = {
    + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
    + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
    +};
    +
    static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
    QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
    QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
    @@ -774,6 +808,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
    .phy_status = PHYSTATUS,
    };

    +static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
    + .lanes = 2,
    +
    + .tables = {
    + .serdes = sm8150_ufsphy_serdes,
    + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
    + .tx = sm8150_ufsphy_tx,
    + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
    + .rx = sm8150_ufsphy_rx,
    + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
    + .pcs = sm8150_ufsphy_pcs,
    + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
    + },
    + .tables_hs_g4 = {
    + .tx = sm8250_ufsphy_hs_g4_tx,
    + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
    + .rx = sm8250_ufsphy_hs_g4_rx,
    + .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
    + .pcs = sm8250_ufsphy_hs_g4_pcs,
    + .pcs_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_pcs),
    + },
    + .clk_list = sdm845_ufs_phy_clk_l,
    + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
    + .vreg_list = qmp_phy_vreg_l,
    + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
    + .regs = sm8150_ufsphy_regs_layout,
    +
    + .start_ctrl = SERDES_START,
    + .pwrdn_ctrl = SW_PWRDN,
    + .phy_status = PHYSTATUS,
    +};
    +
    static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
    .lanes = 2,

    @@ -1226,7 +1292,7 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
    .data = &sm8150_ufsphy_cfg,
    }, {
    .compatible = "qcom,sm8250-qmp-ufs-phy",
    - .data = &sm8150_ufsphy_cfg,
    + .data = &sm8250_ufsphy_cfg,
    }, {
    .compatible = "qcom,sm8350-qmp-ufs-phy",
    .data = &sm8350_ufsphy_cfg,
    --
    2.25.1
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