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    SubjectRe: [PATCH v10 107/108] KVM: x86: design documentation on TDX support of x86 KVM TDP MMU
    On Sat, Oct 29, 2022 at 11:23:48PM -0700, isaku.yamahata@intel.com wrote:
    > +During TDX non-root operation (i.e. guest TD), memory accesses can be qualified
    > +as either shared or private, based on the value of a new SHARED bit in the Guest
    > +Physical Address (GPA). The CPU translates shared GPAs using the usual VMX EPT
    > +(Extended Page Table) or "Shared EPT" (in this document), which resides in the
    > +host VMM memory. The Shared EPT is directly managed by the host VMM - the same
    > +as with the current VMX. Since guest TDs usually require I/O, and the data
    > +exchange needs to be done via shared memory, thus KVM needs to use the current
    > +EPT functionality even for TDs.

    Strip the last "thus", so it becomes "... via shared memory, KVM needs to use ..."

    > +The following depicts the relationship.
    > +::
    > +
    > + KVM | TDX module
    > + | | |
    > + -------------+---------- | |
    > + | | | |
    > + V V | |
    > + shared GPA private GPA | |
    > + CPU shared EPT pointer KVM private EPT pointer | CPU secure EPT pointer
    > + | | | |
    > + | | | |
    > + V V | V
    > + shared EPT private EPT<-------mirror----->Secure EPT
    > + | | | |
    > + | \--------------------+------\ |
    > + | | | |
    > + V | V V
    > + shared guest page | private guest page
    > + |
    > + |
    > + non-encrypted memory | encrypted memory
    > + |
    > +
    > +shared EPT: CPU and KVM walk with shared GPA
    > + Maintained by the existing code
    > +private EPT: KVM walks with private GPA
    > + Maintained by the twisted existing code
    > +secure EPT: CPU walks with private GPA.
    > + Maintained by TDX module with TDX SEAMCALLs via hooks
    > +

    What about this legend below?

    ---- >8 ----

    diff --git a/Documentation/virt/kvm/tdx-tdp-mmu.rst b/Documentation/virt/kvm/tdx-tdp-mmu.rst
    index 2d91c94e6d8fd7..9ddbf44725f212 100644
    --- a/Documentation/virt/kvm/tdx-tdp-mmu.rst
    +++ b/Documentation/virt/kvm/tdx-tdp-mmu.rst
    @@ -236,12 +236,14 @@ The following depicts the relationship.
    non-encrypted memory | encrypted memory
    |

    -shared EPT: CPU and KVM walk with shared GPA
    - Maintained by the existing code
    -private EPT: KVM walks with private GPA
    - Maintained by the twisted existing code
    -secure EPT: CPU walks with private GPA.
    - Maintained by TDX module with TDX SEAMCALLs via hooks
    +Where:
    +
    + * shared EPT: CPU and KVM walk with shared GPA (maintained by the existing
    + code)
    + * private EPT: KVM walks with private GPA (maintained by the twisted existing
    + code)
    + * secure EPT: CPU walks with private GPA (maintained by TDX module with TDX
    + SEAMCALLs via hooks).


    Tracking private EPT page
    > +Concurrent zapping
    > +------------------
    > +1. read lock
    > +2. freeze the EPT entry (atomically set the value to REMOVED_SPTE)
    > + If other vcpu froze the entry, restart page fault.
    > +3. TLB shootdown
    > +
    > + * send IPI to remote vcpus
    > + * TLB flush (local and remote)
    > +
    > + For each entry update, TLB shootdown is needed because of the
    > + concurrency.

    Concurrency issues?

    Also, as I have iterated several times before, you need to add the
    documentation to KVM table of contents (index):

    ---- >8 ----
    diff --git a/Documentation/virt/kvm/index.rst b/Documentation/virt/kvm/index.rst
    index cdb8b43ce7970a..ff2db9ab428d3c 100644
    --- a/Documentation/virt/kvm/index.rst
    +++ b/Documentation/virt/kvm/index.rst
    @@ -20,3 +20,4 @@ KVM
    review-checklist

    intel-tdx
    + tdx-tdp-mmu
    Thanks.

    --
    An old man doll... just what I always wanted! - Clara
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