Messages in this thread Patch in this message | | | From | Prabhakar <> | Subject | [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list | Date | Fri, 28 Oct 2022 17:59:16 +0100 |
| |
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. In preparation to add support for RZ/Five SoC add the Andes AX45MP core to the list.
More details about Andes AX45MP core can be found here: [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- v4 -> v5 * Included RB tag from Conor
v3 -> v4 * No change
v2 -> v3 * Included RB tag from Geert
v1 -> v2 * Included ack from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index ae7963e99225..2bf91829c8de 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,6 +28,7 @@ properties: oneOf: - items: - enum: + - andestech,ax45mp - canaan,k210 - sifive,bullet0 - sifive,e5 -- 2.25.1
| |