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SubjectRe: [PATCH] x86: intel_epb: Set Alder Lake N and Raptor Lake P normal EPB
On Fri, Oct 28, 2022 at 12:01 AM Srinivas Pandruvada
<srinivas.pandruvada@linux.intel.com> wrote:
>
> Intel processors support additional software hint called EPB ("Energy
> Performance Bias") to guide the hardware heuristic of power management
> features to favor increasing dynamic performance or conserve energy
> consumption.
>
> Since this EPB hint is processor specific, the same value of hint can
> result in different behavior across generations of processors.
>
> commit 4ecc933b7d1f ("x86: intel_epb: Allow model specific normal EPB
> value")' introduced capability to update the default power up EPB
> based on the CPU model and updated the default EPB to 7 for Alder Lake
> mobile CPUs.
>
> The same change is required for other Alder Lake-N and Raptor Lake-P
> mobile CPUs as the current default of 6 results in higher uncore power
> consumption. This increase in power is related to memory clock
> frequency setting based on the EPB value.
>
> Depending on the EPB the minimum memory frequency is set by the
> firmware. At EPB = 7, the minimum memory frequency is 1/4th compared to
> EPB = 6. This results in significant power saving for idle and
> semi-idle workload on a Chrome platform.
>
> For example Change in power and performance from EPB change from 6 to 7
> on Alder Lake-N:
>
> Workload Performance diff (%) power diff
> ----------------------------------------------------
> VP9 FHD30 0 (FPS) -218 mw
> Google meet 0 (FPS) -385 mw
>
> This 200+ mw power saving is very significant for mobile platform for
> battery life and thermal reasons.
>
> But as the workload demands more memory bandwidth, the memory frequency
> will be increased very fast. There is no power savings for such busy
> workloads.
>
> For example:
>
> Workload Performance diff (%) from EPB 6 to 7
> -------------------------------------------------------
> Speedometer 2.0 -0.8
> WebGL Aquarium 10K
> Fish -0.5
> Unity 3D 2018 0.2
> WebXPRT3 -0.5
>
> There are run to run variations for performance scores for
> such busy workloads. So the difference is not significant.
>
> Add a new define ENERGY_PERF_BIAS_NORMAL_POWERSAVE for EPB 7
> and use it for Alder Lake-N and Raptor Lake-P mobile CPUs.
>
> This modification is done originally by
> Jeremy Compostella <jeremy.compostella@intel.com>.
>
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>

Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

> ---
> arch/x86/include/asm/msr-index.h | 1 +
> arch/x86/kernel/cpu/intel_epb.c | 7 ++++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 10ac52705892..a3eb4d3e70b8 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -796,6 +796,7 @@
> #define ENERGY_PERF_BIAS_PERFORMANCE 0
> #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
> #define ENERGY_PERF_BIAS_NORMAL 6
> +#define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7
> #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
> #define ENERGY_PERF_BIAS_POWERSAVE 15
>
> diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c
> index fbaf12e43f41..3b8476158236 100644
> --- a/arch/x86/kernel/cpu/intel_epb.c
> +++ b/arch/x86/kernel/cpu/intel_epb.c
> @@ -204,7 +204,12 @@ static int intel_epb_offline(unsigned int cpu)
> }
>
> static const struct x86_cpu_id intel_epb_normal[] = {
> - X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 7),
> + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,
> + ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
> + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,
> + ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
> + X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,
> + ENERGY_PERF_BIAS_NORMAL_POWERSAVE),
> {}
> };
>
> --
> 2.31.1
>

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