Messages in this thread | | | Date | Fri, 28 Oct 2022 09:46:34 -0500 | Subject | Re: [PATCH 3/5] cxl/pci: Discover and cache pointer to RCD dport's CXL RAS registers | From | Terry Bowman <> |
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Hi Ariel,
On 10/28/22 07:53, Ariel.Sibley@microchip.com wrote: >> -----Original Message----- >> From: Terry Bowman <terry.bowman@amd.com> >> Sent: Friday, October 21, 2022 3:56 PM >> To: alison.schofield@intel.com; vishal.l.verma@intel.com; dave.jiang@intel.com; ira.weiny@intel.com; >> bwidawsk@kernel.org; dan.j.williams@intel.com >> Cc: terry.bowman@amd.com; linux-cxl@vger.kernel.org; linux-kernel@vger.kernel.org; bhelgaas@google.com; >> rafael@kernel.org; lenb@kernel.org; Jonathan.Cameron@huawei.com; dave@stgolabs.net; rrichter@amd.com >> Subject: [PATCH 3/5] cxl/pci: Discover and cache pointer to RCD dport's CXL RAS registers >> >> CXL RAS information resides in a RAS capability structure located in >> CXL.cache and CXL.mem registers.[1] The RAS capability provides CXL >> specific error information that can be helpful in debugging. This >> information is not currently logged but needs to be logged during PCIe AER >> error handling. >> >> Update the CXL driver to find and cache a pointer to the CXL RAS >> capability. The RAS registers resides in the downport's component register >> block. Note:RAS registers are not in the upport. The component registers >> can be found by first using the RCRB to goto the downport. Next, the >> downport's 64-bit BAR[0] will point to the component register block. > > I realize this patch is for dport only, but regarding "Note:RAS registers > are not in the upport.", the upstream port also has RAS registers. >
Correct. Thanks for pointing this out.
> Per CXL 3.0 Section 12.2.1.2 RCD Upstream Port-detected Errors: > "1. If a CXL.cache or CXL.mem logic block in UPZ detects a protocol or link > error, the block shall log the error in the CXL RAS Capability (see Section > 8.2.4.16)."
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