Messages in this thread | | | Date | Thu, 27 Oct 2022 14:48:44 +0200 | Subject | Re: [PATCH v1 2/5] clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdsc | From | Konrad Dybcio <> |
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On 27/10/2022 14:34, Robert Foss wrote: > All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, > so it should be enabled here. > > This feature enables registers to maintain their state after > dis/re-enabling the GDSC. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Konrad
> drivers/clk/qcom/dispcc-sm8250.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c > index 180ac2726f7e..a7606580cf22 100644 > --- a/drivers/clk/qcom/dispcc-sm8250.c > +++ b/drivers/clk/qcom/dispcc-sm8250.c > @@ -1137,7 +1137,7 @@ static struct gdsc mdss_gdsc = { > .name = "mdss_gdsc", > }, > .pwrsts = PWRSTS_OFF_ON, > - .flags = HW_CTRL, > + .flags = HW_CTRL | RETAIN_FF_ENABLE, > }; > > static struct clk_regmap *disp_cc_sm8250_clocks[] = {
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