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    Subject[RFC v2 7/7] arm64: dts: mt7986: add Bananapi R3
    Date
    From: Frank Wunderlich <frank-w@public-files.de>

    Add support for Bananapi R3 SBC.

    - SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
    - all rj45 ports and both SFP working (eth1/lan4)
    - all USB-Ports + SIM-Slot tested
    - i2c and all uarts tested
    - wifi tested

    Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
    ---
    SPI-NAND/NOR switched (CS by sw5/C) not yet included
    this is done with DT-Overlays in my tree, but i have no idea yet,
    how to upstream

    break some lines in wifi-eeprom-data because of checkpatch warnings.
    originally there were 8 x int32 per line

    changes:

    v2:
    - remove pcie to be added later (discussion about clocks)
    - some fixes based on suggestions on ML
    - add key suffix like it's done in mt7622-bpi-r64 devicetree
    - add dash in sfp node names
    - use reg as unit for switch-node
    - drop "-3-4" suffix from i2c-pins node name
    - fix order in Makefile
    ---
    arch/arm64/boot/dts/mediatek/Makefile | 2 +
    .../mediatek/mt7986a-bananapi-bpi-r3-emmc.dts | 34 +
    .../mediatek/mt7986a-bananapi-bpi-r3-sd.dts | 29 +
    .../dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi | 593 ++++++++++++++++++
    4 files changed, 658 insertions(+)
    create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts
    create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts
    create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi

    diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
    index 0ec90cb3ef28..e8902f2cc58f 100644
    --- a/arch/arm64/boot/dts/mediatek/Makefile
    +++ b/arch/arm64/boot/dts/mediatek/Makefile
    @@ -7,6 +7,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
    dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
    dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
    dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
    +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtb
    +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtb
    dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
    dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
    dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
    diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts
    new file mode 100644
    index 000000000000..859b4180ca11
    --- /dev/null
    +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dts
    @@ -0,0 +1,34 @@
    +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
    +/*
    + * Copyright (C) 2021 MediaTek Inc.
    + * Author: Sam.Shih <sam.shih@mediatek.com>
    + */
    +
    +/dts-v1/;
    +#include <dt-bindings/input/input.h>
    +#include <dt-bindings/gpio/gpio.h>
    +
    +#include "mt7986a-bananapi-bpi-r3.dtsi"
    +
    +/ {
    + model = "Bananapi BPI-R3 (emmc)";
    +};
    +
    +&mmc0 {
    + pinctrl-names = "default", "state_uhs";
    + pinctrl-0 = <&mmc0_pins_default>;
    + pinctrl-1 = <&mmc0_pins_uhs>;
    + bus-width = <8>;
    + max-frequency = <200000000>;
    + cap-mmc-highspeed;
    + mmc-hs200-1_8v;
    + mmc-hs400-1_8v;
    + hs400-ds-delay = <0x14014>;
    + vmmc-supply = <&reg_3p3v>;
    + vqmmc-supply = <&reg_1p8v>;
    + non-removable;
    + no-sd;
    + no-sdio;
    + status = "okay";
    +};
    +
    diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts
    new file mode 100644
    index 000000000000..57200407ab86
    --- /dev/null
    +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dts
    @@ -0,0 +1,29 @@
    +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
    +/*
    + * Copyright (C) 2021 MediaTek Inc.
    + * Author: Sam.Shih <sam.shih@mediatek.com>
    + */
    +
    +/dts-v1/;
    +#include <dt-bindings/input/input.h>
    +#include <dt-bindings/gpio/gpio.h>
    +
    +#include "mt7986a-bananapi-bpi-r3.dtsi"
    +
    +/ {
    + model = "Bananapi BPI-R3 (sdmmc)";
    +};
    +
    +&mmc0 {
    + //sdcard
    + pinctrl-names = "default", "state_uhs";
    + pinctrl-0 = <&mmc0_pins_default>;
    + pinctrl-1 = <&mmc0_pins_uhs>;
    + bus-width = <4>;
    + max-frequency = <52000000>;
    + cap-sd-highspeed;
    + vmmc-supply = <&reg_3p3v>;
    + vqmmc-supply = <&reg_1p8v>;
    + status = "okay";
    +};
    +
    diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi
    new file mode 100644
    index 000000000000..fc100c3a6415
    --- /dev/null
    +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dtsi
    @@ -0,0 +1,593 @@
    +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
    +/*
    + * Copyright (C) 2021 MediaTek Inc.
    + * Authors: Sam.Shih <sam.shih@mediatek.com>
    + * Frank Wunderlich <frank-w@public-files.de>
    + * Daniel Golle <daniel@makrotopia.org>
    + */
    +
    +/dts-v1/;
    +#include <dt-bindings/input/input.h>
    +#include <dt-bindings/gpio/gpio.h>
    +#include <dt-bindings/leds/common.h>
    +
    +#include "mt7986a.dtsi"
    +
    +/ {
    + model = "Bananapi BPI-R3";
    + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
    +
    + aliases {
    + serial0 = &uart0;
    + ethernet0 = &gmac0;
    + ethernet1 = &gmac1;
    + };
    +
    + chosen {
    + stdout-path = "serial0:115200n8";
    + };
    +
    + gpio-keys {
    + compatible = "gpio-keys";
    +
    + factory-key {
    + label = "reset";
    + linux,code = <KEY_RESTART>;
    + gpios = <&pio 9 GPIO_ACTIVE_LOW>;
    + };
    +
    + wps-key {
    + label = "wps";
    + linux,code = <KEY_WPS_BUTTON>;
    + gpios = <&pio 10 GPIO_ACTIVE_LOW>;
    + };
    + };
    +
    + /* i2c of the left SFP cage (wan) */
    + i2c_sfp1: i2c-gpio-0 {
    + compatible = "i2c-gpio";
    + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    + i2c-gpio,delay-us = <2>;
    + #address-cells = <1>;
    + #size-cells = <0>;
    + };
    +
    + /* i2c of the right SFP cage (lan) */
    + i2c_sfp2: i2c-gpio-1 {
    + compatible = "i2c-gpio";
    + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
    + i2c-gpio,delay-us = <2>;
    + #address-cells = <1>;
    + #size-cells = <0>;
    + };
    +
    + leds {
    + compatible = "gpio-leds";
    +
    + green_led: led-0 {
    + color = <LED_COLOR_ID_GREEN>;
    + function = LED_FUNCTION_POWER;
    + gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
    + default-state = "on";
    + };
    +
    + blue_led: led-1 {
    + color = <LED_COLOR_ID_BLUE>;
    + function = LED_FUNCTION_STATUS;
    + gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
    + default-state = "off";
    + };
    + };
    +
    + memory@40000000 {
    + device_type = "memory";
    + reg = <0 0x40000000 0 0x40000000>;
    + };
    +
    + reg_1p8v: regulator-1p8v {
    + compatible = "regulator-fixed";
    + regulator-name = "fixed-1.8V";
    + regulator-min-microvolt = <1800000>;
    + regulator-max-microvolt = <1800000>;
    + regulator-boot-on;
    + regulator-always-on;
    + };
    +
    + reg_3p3v: regulator-3p3v {
    + compatible = "regulator-fixed";
    + regulator-name = "fixed-3.3V";
    + regulator-min-microvolt = <3300000>;
    + regulator-max-microvolt = <3300000>;
    + regulator-boot-on;
    + regulator-always-on;
    + };
    +
    + reg_5v: regulator-5v {
    + compatible = "regulator-fixed";
    + regulator-name = "fixed-5V";
    + regulator-min-microvolt = <5000000>;
    + regulator-max-microvolt = <5000000>;
    + regulator-boot-on;
    + regulator-always-on;
    + };
    +
    + /* left SFP cage (wan) */
    + sfp1: sfp-1 {
    + compatible = "sff,sfp";
    + i2c-bus = <&i2c_sfp1>;
    + los-gpio = <&pio 46 GPIO_ACTIVE_HIGH>;
    + moddef0-gpio = <&pio 49 GPIO_ACTIVE_LOW>;
    + tx-disable-gpio = <&pio 20 GPIO_ACTIVE_HIGH>;
    + tx-fault-gpio = <&pio 7 GPIO_ACTIVE_HIGH>;
    + };
    +
    + /* right SFP cage (lan) */
    + sfp2: sfp-2 {
    + compatible = "sff,sfp";
    + i2c-bus = <&i2c_sfp2>;
    + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
    + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
    + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
    + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
    + };
    +};
    +
    +&crypto {
    + status = "okay";
    +};
    +
    +&eth {
    + status = "okay";
    +
    + gmac0: mac@0 {
    + compatible = "mediatek,eth-mac";
    + reg = <0>;
    + phy-mode = "2500base-x";
    +
    + fixed-link {
    + speed = <2500>;
    + full-duplex;
    + pause;
    + };
    + };
    +
    + gmac1: mac@1 {
    + compatible = "mediatek,eth-mac";
    + reg = <1>;
    + phy-mode = "2500base-x";
    + sfp = <&sfp1>;
    + managed = "in-band-status";
    + };
    +
    + mdio: mdio-bus {
    + #address-cells = <1>;
    + #size-cells = <0>;
    + };
    +};
    +
    +&mdio {
    + switch: switch@31 {
    + compatible = "mediatek,mt7531";
    + reg = <31>;
    + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
    + };
    +};
    +
    +&i2c0 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&i2c_pins>;
    + status = "okay";
    +};
    +
    +&pio {
    + i2c_pins: i2c-pins {
    + mux {
    + function = "i2c";
    + groups = "i2c";
    + };
    + };
    +
    + mmc0_pins_default: mmc0-pins {
    + mux {
    + function = "emmc";
    + groups = "emmc_51";
    + };
    + conf-cmd-dat {
    + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
    + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
    + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
    + input-enable;
    + drive-strength = <4>;
    + mediatek,pull-up-adv = <1>; /* pull-up 10K */
    + };
    + conf-clk {
    + pins = "EMMC_CK";
    + drive-strength = <6>;
    + mediatek,pull-down-adv = <2>; /* pull-down 50K */
    + };
    + conf-ds {
    + pins = "EMMC_DSL";
    + mediatek,pull-down-adv = <2>; /* pull-down 50K */
    + };
    + conf-rst {
    + pins = "EMMC_RSTB";
    + drive-strength = <4>;
    + mediatek,pull-up-adv = <1>; /* pull-up 10K */
    + };
    + };
    +
    + mmc0_pins_uhs: mmc0-uhs-pins {
    + mux {
    + function = "emmc";
    + groups = "emmc_51";
    + };
    + conf-cmd-dat {
    + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
    + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
    + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
    + input-enable;
    + drive-strength = <4>;
    + mediatek,pull-up-adv = <1>; /* pull-up 10K */
    + };
    + conf-clk {
    + pins = "EMMC_CK";
    + drive-strength = <6>;
    + mediatek,pull-down-adv = <2>; /* pull-down 50K */
    + };
    + conf-ds {
    + pins = "EMMC_DSL";
    + mediatek,pull-down-adv = <2>; /* pull-down 50K */
    + };
    + conf-rst {
    + pins = "EMMC_RSTB";
    + drive-strength = <4>;
    + mediatek,pull-up-adv = <1>; /* pull-up 10K */
    + };
    + };
    +
    + spi_flash_pins: spi-flash-pins {
    + mux {
    + function = "spi";
    + groups = "spi0", "spi0_wp_hold";
    + };
    + };
    +
    + spic_pins: spic-pins {
    + mux {
    + function = "spi";
    + groups = "spi1_0";
    + };
    + };
    +
    + uart1_pins: uart1-pins {
    + mux {
    + function = "uart";
    + groups = "uart1_rx_tx";
    + };
    + };
    +
    + uart2_pins: uart2-pins {
    + mux {
    + function = "uart";
    + groups = "uart2_0_rx_tx";
    + };
    + };
    +
    + wf_2g_5g_pins: wf-2g-5g-pins {
    + mux {
    + function = "wifi";
    + groups = "wf_2g", "wf_5g";
    + };
    + conf {
    + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
    + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
    + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
    + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
    + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
    + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
    + "WF1_TOP_CLK", "WF1_TOP_DATA";
    + drive-strength = <4>;
    + };
    + };
    +
    + wf_dbdc_pins: wf-dbdc-pins {
    + mux {
    + function = "wifi";
    + groups = "wf_dbdc";
    + };
    + conf {
    + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
    + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
    + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
    + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
    + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
    + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
    + "WF1_TOP_CLK", "WF1_TOP_DATA";
    + drive-strength = <4>;
    + };
    + };
    +
    + wf_led_pins: wf-led-pins {
    + mux {
    + function = "led";
    + groups = "wifi_led";
    + };
    + };
    +};
    +
    +&spi0 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&spi_flash_pins>;
    + cs-gpios = <0>, <0>;
    + status = "okay";
    +};
    +
    +&spi1 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&spic_pins>;
    + cs-gpios = <0>, <0>;
    + status = "okay";
    +};
    +
    +&ssusb {
    + vusb33-supply = <&reg_3p3v>;
    + vbus-supply = <&reg_5v>;
    + status = "okay";
    +};
    +
    +&switch {
    + ports {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + port@0 {
    + reg = <0>;
    + label = "wan";
    + };
    +
    + port@1 {
    + reg = <1>;
    + label = "lan0";
    + };
    +
    + port@2 {
    + reg = <2>;
    + label = "lan1";
    + };
    +
    + port@3 {
    + reg = <3>;
    + label = "lan2";
    + };
    +
    + port@4 {
    + reg = <4>;
    + label = "lan3";
    + };
    +
    + port5: port@5 {
    + reg = <5>;
    + label = "lan4";
    + phy-mode = "2500base-x";
    + sfp = <&sfp2>;
    + managed = "in-band-status";
    + };
    +
    + port@6 {
    + reg = <6>;
    + label = "cpu";
    + ethernet = <&gmac0>;
    + phy-mode = "2500base-x";
    +
    + fixed-link {
    + speed = <2500>;
    + full-duplex;
    + pause;
    + };
    + };
    + };
    +};
    +
    +&trng {
    + status = "okay";
    +};
    +
    +&uart0 {
    + status = "okay";
    +};
    +
    +&uart1 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&uart1_pins>;
    + status = "okay";
    +};
    +
    +&uart2 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&uart2_pins>;
    + status = "okay";
    +};
    +
    +&usb_phy {
    + status = "okay";
    +};
    +
    +&watchdog {
    + status = "okay";
    +};
    +
    +&wifi {
    + status = "okay";
    + pinctrl-names = "default", "dbdc";
    + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
    + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
    +
    + mediatek,eeprom-data = <0x86790900 0xc4326 0x60000000 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1000000
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x800 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x24649090 0x280000 0x5100000 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    + 0x21e00 0x21e0002 0x1e00021e 0x22800 0x2280002 0x28000228 0x00 0x00
    + 0x00 0x00 0x00 0x00 0x00 0x00 0x8080 0x8080fdf7
    + 0x903150d 0x80808080 0x80808080 0x5050d0d 0x1313c6c6 0xc3c3c200
    + 0xc200c2 0x8182
    + 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200
    + 0x81818285 0x858787c2
    + 0xc2000081 0x82858587 0x87c2c200 0x818285 0x858787c2 0xc2000081
    + 0x82858587 0x87c4c4c2
    + 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0
    + 0x81828484 0xc3
    + 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081
    + 0x82848486 0x86c3c3c3
    + 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183
    + 0x83868622 0x28002228
    + 0x222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd
    + 0xdddddddd 0xdddddddd
    + 0xeeeeeecc 0xccccdddd 0xdddddddd 0x4a5662 0x4a 0x56620000 0x4a5662
    + 0x4a
    + 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326
    + 0x26262626 0x26262600
    + 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
    + 0x00 0xf0f0cc00
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    + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
    +};
    +
    --
    2.34.1
    \
     
     \ /
      Last update: 2022-10-26 11:38    [W:3.457 / U:0.428 seconds]
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