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    SubjectRe: [RFC RESEND PATCH 0/2] RZ/G2UL separate out SoC specific parts
    Hi Geert.

    Thank you for the review.

    On Tue, Oct 25, 2022 at 1:42 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
    >
    > Hi Prabhakar,
    >
    > (now replying to the latest version)
    >
    > On Mon, Oct 17, 2022 at 11:12 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
    > > This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
    > > so that this can be shared with the RZ/Five SoC.
    > >
    > > Implementation is based on the discussion [0] where I have used option#2.
    > >
    > > The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
    > > identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
    > > created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
    > > (r9a07g043F.dtsi)
    >
    > Thanks for your series!
    >
    > > Sending this as an RFC to get some feedback.
    > >
    > > r9a07g043f.dtsi will look something like below:
    > >
    > > #include <dt-bindings/interrupt-controller/irq.h>
    > >
    > > #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
    > > #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
    >
    > Originally, when I assumed incorrectly that dtc does not support
    > arithmetic, I used "nr" and "na" in the macro I proposed to mean RISC-V
    > ("r") resp. ARM ("a") interrupt number. Apparently the names stuck,
    > although the second parameter now has a completely different meaning ;-)
    >
    > However, as the NCEPLIC does support interrupt flags, unlike the SiFive
    > PLIC, there is no need to have the flags parameter in the macro.
    >
    > Moreover, it looks like the SOC_PERIPHERAL_IRQ_NUMBER()
    > intermediate is not needed, so you can just write:
    >
    > #define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
    >
    Agreed, I'll change it as per your suggestion and send a v2.

    Cheers,
    Prabhakar

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