Messages in this thread | | | From | "Lad, Prabhakar" <> | Date | Tue, 25 Oct 2022 17:10:55 +0100 | Subject | Re: [RFC RESEND PATCH 1/2] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property |
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Hi Geert,
Thank you for the review.
On Tue, Oct 25, 2022 at 1:28 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Oct 17, 2022 at 11:12 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so > > that we can share the common parts of the SoC DTSI with the RZ/Five > > (RISC-V) SoC and the RZ/G2UL (ARM64) SoC. > > > > This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL > > (ARM64) SoC specific parts. No functional changes (same DTB). > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > @@ -0,0 +1,12 @@ > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +/* > > + * Device Tree Source for the RZ/G2UL SoC > > + * > > + * Copyright (C) 2022 Renesas Electronics Corp. > > + */ > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > +#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr na > > s/na/flags/ > > Originally, when I assumed incorrectly that dtc does not support > arithmetic, I used "nr" and "na" in the macro I proposed to mean RISC-V > ("r") resp. ARM ("a") interrupt number. Apparently the names stuck, > although the second parameter now has a completely different meaning ;-) > > However, as the NCEPLIC does support interrupt flags, unlike the SiFive > PLIC, there is no need to have the flags parameter in the macro. > Ok, I'll drop the second parameter.
Cheers, Prabhakar
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