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    Subject[PATCH v3 01/12] dt-bindings: display/msm: Add binding for SC8280XP MDSS
    Date
    From: Bjorn Andersson <bjorn.andersson@linaro.org>

    Add binding for the display subsystem and display processing unit in the
    Qualcomm SC8280XP platform.

    Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
    Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
    ---

    Changes since v2:
    - Cleaned up description and interconnect definitions
    - Added opp-table

    .../bindings/display/msm/dpu-sc8280xp.yaml | 287 ++++++++++++++++++
    1 file changed, 287 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml

    diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
    new file mode 100644
    index 000000000000..24e7a1562fe7
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml
    @@ -0,0 +1,287 @@
    +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
    +%YAML 1.2
    +---
    +$id: http://devicetree.org/schemas/display/msm/dpu-sc8280xp.yaml#
    +$schema: http://devicetree.org/meta-schemas/core.yaml#
    +
    +title: Qualcomm Display Processing Unit for SC8280XP
    +
    +maintainers:
    + - Bjorn Andersson <bjorn.andersson@linaro.org>
    +
    +description:
    + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
    + sub-blocks like DPU display controller, DSI and DP interfaces etc.
    +
    +properties:
    + compatible:
    + const: qcom,sc8280xp-mdss
    +
    + reg:
    + maxItems: 1
    +
    + reg-names:
    + const: mdss
    +
    + power-domains:
    + maxItems: 1
    +
    + clocks:
    + items:
    + - description: Display AHB clock from gcc
    + - description: Display AHB clock from dispcc
    + - description: Display core clock
    +
    + clock-names:
    + items:
    + - const: iface
    + - const: ahb
    + - const: core
    +
    + interrupts:
    + maxItems: 1
    +
    + interrupt-controller: true
    +
    + "#address-cells": true
    +
    + "#size-cells": true
    +
    + "#interrupt-cells":
    + const: 1
    +
    + iommus:
    + items:
    + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
    +
    + ranges: true
    +
    + interconnects:
    + items:
    + - description: Interconnect path for first data bus
    + - description: Interconnect path for second data bus
    +
    + interconnect-names:
    + items:
    + - const: mdp0-mem
    + - const: mdp1-mem
    +
    + resets:
    + items:
    + - description: MDSS_CORE reset
    +
    +patternProperties:
    + "^display-controller@[0-9a-f]+$":
    + type: object
    + description: Node containing the properties of DPU.
    + additionalProperties: false
    +
    + properties:
    + compatible:
    + const: qcom,sc8280xp-dpu
    +
    + reg:
    + items:
    + - description: Address offset and size for mdp register set
    + - description: Address offset and size for vbif register set
    +
    + reg-names:
    + items:
    + - const: mdp
    + - const: vbif
    +
    + clocks:
    + items:
    + - description: Display hf axi clock
    + - description: Display sf axi clock
    + - description: Display ahb clock
    + - description: Display lut clock
    + - description: Display core clock
    + - description: Display vsync clock
    +
    + clock-names:
    + items:
    + - const: bus
    + - const: nrt_bus
    + - const: iface
    + - const: lut
    + - const: core
    + - const: vsync
    +
    + interrupts:
    + maxItems: 1
    +
    + power-domains:
    + maxItems: 1
    +
    + operating-points-v2: true
    + opp-table:
    + type: object
    +
    + ports:
    + $ref: /schemas/graph.yaml#/properties/ports
    + description: |
    + Contains the list of output ports from DPU device. These ports
    + connect to interfaces that are external to the DPU hardware,
    + such as DSI, DP etc. Each output port contains an endpoint that
    + describes how it is connected to an external interface.
    +
    + patternProperties:
    + '^port@[0-8]$':
    + $ref: /schemas/graph.yaml#/properties/port
    + description: DPU interfaces
    +
    + required:
    + - compatible
    + - reg
    + - reg-names
    + - clocks
    + - interrupts
    + - power-domains
    + - operating-points-v2
    + - ports
    +
    +required:
    + - compatible
    + - reg
    + - reg-names
    + - power-domains
    + - clocks
    + - interrupts
    + - interrupt-controller
    + - iommus
    + - ranges
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
    + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    + #include <dt-bindings/interconnect/qcom,sc8280xp.h>
    + #include <dt-bindings/power/qcom-rpmpd.h>
    +
    + display-subsystem@ae00000 {
    + compatible = "qcom,sc8280xp-mdss";
    + reg = <0x0ae00000 0x1000>;
    + reg-names = "mdss";
    +
    + power-domains = <&dispcc0 MDSS_GDSC>;
    +
    + clocks = <&gcc GCC_DISP_AHB_CLK>,
    + <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
    + <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
    + clock-names = "iface",
    + "ahb",
    + "core";
    +
    + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
    + assigned-clock-rates = <460000000>;
    +
    + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
    +
    + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-controller;
    + #interrupt-cells = <1>;
    +
    + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
    + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
    + interconnect-names = "mdp0-mem", "mdp1-mem";
    +
    + iommus = <&apps_smmu 0x1000 0x402>;
    +
    + #address-cells = <1>;
    + #size-cells = <1>;
    + ranges;
    +
    + display-controller@ae01000 {
    + compatible = "qcom,sc8280xp-dpu";
    + reg = <0x0ae01000 0x8f000>,
    + <0x0aeb0000 0x2008>;
    + reg-names = "mdp", "vbif";
    +
    + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
    + <&gcc GCC_DISP_SF_AXI_CLK>,
    + <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
    + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
    + <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
    + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
    + clock-names = "bus",
    + "nrt_bus",
    + "iface",
    + "lut",
    + "core",
    + "vsync";
    +
    + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
    + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
    + assigned-clock-rates = <460000000>,
    + <19200000>;
    +
    + operating-points-v2 = <&mdss0_mdp_opp_table>;
    + power-domains = <&rpmhpd SC8280XP_MMCX>;
    +
    + interrupt-parent = <&mdss0>;
    + interrupts = <0>;
    +
    + ports {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + port@0 {
    + reg = <0>;
    + endpoint {
    + remote-endpoint = <&mdss0_dp0_in>;
    + };
    + };
    +
    + port@4 {
    + reg = <4>;
    + endpoint {
    + remote-endpoint = <&mdss0_dp1_in>;
    + };
    + };
    +
    + port@5 {
    + reg = <5>;
    + endpoint {
    + remote-endpoint = <&mdss0_dp3_in>;
    + };
    + };
    +
    + port@6 {
    + reg = <6>;
    + endpoint {
    + remote-endpoint = <&mdss0_dp2_in>;
    + };
    + };
    + };
    +
    + mdss0_mdp_opp_table: opp-table {
    + compatible = "operating-points-v2";
    +
    + opp-200000000 {
    + opp-hz = /bits/ 64 <200000000>;
    + required-opps = <&rpmhpd_opp_low_svs>;
    + };
    +
    + opp-300000000 {
    + opp-hz = /bits/ 64 <300000000>;
    + required-opps = <&rpmhpd_opp_svs>;
    + };
    +
    + opp-345000000 {
    + opp-hz = /bits/ 64 <345000000>;
    + required-opps = <&rpmhpd_opp_svs_l1>;
    + };
    +
    + opp-460000000 {
    + opp-hz = /bits/ 64 <460000000>;
    + required-opps = <&rpmhpd_opp_nom>;
    + };
    + };
    + };
    + };
    +...
    +
    --
    2.37.3
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