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    Subject[PATCH 5.10 354/390] clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
    Date
    From: Quanyang Wang <quanyang.wang@windriver.com>

    [ Upstream commit 30eaf02149ecc3c5815e45d27187bf09e925071d ]

    The function zynqmp_pll_round_rate is used to find a most appropriate
    PLL frequency which the hardware can generate according to the desired
    frequency. For example, if the desired frequency is 297MHz, considering
    the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz)
    of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5).

    There are two problems with the current code of zynqmp_pll_round_rate:

    1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate
    when the parameter "rate" is an integer multiple of *prate, in other words,
    if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which
    is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz
    and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and
    just return 660MHz, and this will cause clk_calc_new_rates failure since
    zynqmp_pll_round_rate returns an invalid rate out of its boundaries.

    2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk
    that zynqmp_pll_round_rate returns an invalid rate because the function
    DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent
    clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz,
    this function will return 1499999985Hz by using the formula below:
    value = *prate * DIV_ROUND_CLOSEST(rate, *prate)).
    This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN.
    because DIV_ROUND_CLOSEST makes some loss in the fractional part.

    Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
    Link: https://lore.kernel.org/r/20220826142030.213805-1-quanyang.wang@windriver.com
    Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/zynqmp/pll.c | 31 +++++++++++++++----------------
    1 file changed, 15 insertions(+), 16 deletions(-)

    diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
    index abe6afbf3407..2ae7f9129b07 100644
    --- a/drivers/clk/zynqmp/pll.c
    +++ b/drivers/clk/zynqmp/pll.c
    @@ -99,26 +99,25 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    unsigned long *prate)
    {
    u32 fbdiv;
    - long rate_div, f;
    + u32 mult, div;

    - /* Enable the fractional mode if needed */
    - rate_div = (rate * FRAC_DIV) / *prate;
    - f = rate_div % FRAC_DIV;
    - if (f) {
    - if (rate > PS_PLL_VCO_MAX) {
    - fbdiv = rate / PS_PLL_VCO_MAX;
    - rate = rate / (fbdiv + 1);
    - }
    - if (rate < PS_PLL_VCO_MIN) {
    - fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
    - rate = rate * fbdiv;
    - }
    - return rate;
    + /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */
    + if (rate > PS_PLL_VCO_MAX) {
    + div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);
    + rate = rate / div;
    + }
    + if (rate < PS_PLL_VCO_MIN) {
    + mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
    + rate = rate * mult;
    }

    fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
    - fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
    - return *prate * fbdiv;
    + if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
    + fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
    + rate = *prate * fbdiv;
    + }
    +
    + return rate;
    }

    /**
    --
    2.35.1


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