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    Subject[PATCH 5.10 129/390] spi: s3c64xx: Fix large transfers with DMA
    Date
    From: Vincent Whitchurch <vincent.whitchurch@axis.com>

    [ Upstream commit 1224e29572f655facfcd850cf0f0a4784f36a903 ]

    The COUNT_VALUE in the PACKET_CNT register is 16-bit so the maximum
    value is 65535. Asking the driver to transfer a larger size currently
    leads to the DMA transfer timing out. Implement ->max_transfer_size()
    and have the core split the transfer as needed.

    Fixes: 230d42d422e7 ("spi: Add s3c64xx SPI Controller driver")
    Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
    Link: https://lore.kernel.org/r/20220927112117.77599-5-vincent.whitchurch@axis.com
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/spi/spi-s3c64xx.c | 9 +++++++++
    1 file changed, 9 insertions(+)

    diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
    index dfa7c91e13aa..d435df1b715b 100644
    --- a/drivers/spi/spi-s3c64xx.c
    +++ b/drivers/spi/spi-s3c64xx.c
    @@ -84,6 +84,7 @@
    #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)

    #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
    +#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)

    #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
    #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
    @@ -660,6 +661,13 @@ static int s3c64xx_spi_prepare_message(struct spi_master *master,
    return 0;
    }

    +static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
    +{
    + struct spi_controller *ctlr = spi->controller;
    +
    + return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
    +}
    +
    static int s3c64xx_spi_transfer_one(struct spi_master *master,
    struct spi_device *spi,
    struct spi_transfer *xfer)
    @@ -1135,6 +1143,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
    master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
    master->prepare_message = s3c64xx_spi_prepare_message;
    master->transfer_one = s3c64xx_spi_transfer_one;
    + master->max_transfer_size = s3c64xx_spi_max_transfer_size;
    master->num_chipselect = sci->num_cs;
    master->dma_alignment = 8;
    master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
    --
    2.35.1


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