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    SubjectRe: [PATCH 0/5] cxl: Log downport PCIe AER and CXL RAS error information
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    s/PATCH/RFC/

    On 10/21/22 13:56, Terry Bowman wrote:
    > This patchset adds CXL downport PCI AER and CXL RAS logging to the CXL
    > error handling. This is necessary for communicating CXL HW issues to users.
    > The included patches find and cache pointers to the AER and CXL RAS PCIe
    > capability structures. The cached pointers are then used to display the
    > error information in a later patch. These changes follow the CXL
    > specification, Chapter 8 'Control and Status Registers'.[1]
    >
    > The first patch enables CXL1.1 RCD support through the ACPI _OSC support
    > method.
    >
    > The 2nd and 3rd patches find and map PCIe AER and CXL RAS capabilities.
    >
    > The 4th patch enables AER error reporting.
    >
    > The 5th patch adds functionality to log the PCIe AER and RAS capabilities.
    >
    > TODO work remains to consolidate the HDM and CXL RAS register mapping
    > (patch#3). The current CXL RAS register mapping will be replaced to reuse
    > cxl_probe_component_regs() function as David Jiang and Alison Schofield
    > upstreamed. Should the same be done for the AER registers (patch#2)? The
    > AER registers are not in the component register block but are instead in
    > the downport and upport (RCRB).
    >
    > TODO work remains to add support for upports in some cases here where
    > downport is addressed. For instance, will need another aer_map to support
    > upport AER ?
    >
    > TODO work to support CXL2.0. Should be trivial since aer_cap and aer_stats
    > is member of 'struct pci_dev'.
    >
    > Base is from: https://patchwork.kernel.org/project/cxl/list/?series=686272
    >
    > [1] - https://www.computeexpresslink.org/spec-landing
    >
    > Terry Bowman (5):
    > cxl/acpi: Set ACPI's CXL _OSC to indicate CXL1.1 support
    > cxl/pci: Discover and cache pointer to RCD dport's PCIe AER capability
    > cxl/pci: Discover and cache pointer to RCD dport's CXL RAS registers
    > cxl/pci: Enable RCD dport AER reporting
    > cxl/pci: Log CXL device's PCIe AER and CXL RAS error information
    >
    > drivers/acpi/pci_root.c | 1 +
    > drivers/cxl/acpi.c | 56 +++++++
    > drivers/cxl/core/regs.c | 1 +
    > drivers/cxl/cxl.h | 13 ++
    > drivers/cxl/cxlmem.h | 3 +
    > drivers/cxl/mem.c | 2 +
    > drivers/cxl/pci.c | 319 ++++++++++++++++++++++++++++++++++++++++
    > drivers/pci/pcie/aer.c | 45 +++++-
    > include/linux/pci.h | 4 +
    > 9 files changed, 443 insertions(+), 1 deletion(-)
    >

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