Messages in this thread | | | Date | Fri, 21 Oct 2022 16:55:41 +0800 | Subject | Re: [PATCH 05/15] arm64: dts: imx8mp-evk: enable uart1/3 ports | From | Peng Fan <> |
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Hi Marco,
On 10/20/2022 7:07 PM, Marco Felsch wrote: > Hi Peng, > > On 22-10-20, Peng Fan (OSS) wrote: >> From: Peng Fan <peng.fan@nxp.com> >> >> Enable uart1/3 ports for evk board. >> >> Signed-off-by: Peng Fan <peng.fan@nxp.com> >> --- >> arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts >> index 2e29bb3c041c..366f709f8790 100644 >> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts >> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts >> @@ -428,6 +428,15 @@ &snvs_pwrkey { >> status = "okay"; >> }; >> >> +&uart1 { /* BT */ >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart1>; >> + assigned-clocks = <&clk IMX8MP_CLK_UART1>; >> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; > > I'm curious, what is the default parent and why is this wrong? For the > already exisiting uart2 we don't do that. Same applies for uart3.
The default parent is OSC_24M. The uart2 is for console, so 24M is ok. As I recall, we met issue 24M not able to get higher baudrate.
Regards, Peng. > > Regards, > Marco > > >> + fsl,uart-has-rtscts; >> + status = "okay"; >> +}; >> + >> &uart2 { >> /* console */ >> pinctrl-names = "default"; >> @@ -450,6 +459,15 @@ &usb_dwc3_1 { >> status = "okay"; >> }; >> >> +&uart3 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart3>; >> + assigned-clocks = <&clk IMX8MP_CLK_UART3>; >> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; >> + fsl,uart-has-rtscts; >> + status = "okay"; >> +}; >> + >> &usdhc2 { >> assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; >> assigned-clock-rates = <400000000>; >> @@ -625,6 +643,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >> >; >> }; >> >> + pinctrl_uart1: uart1grp { >> + fsl,pins = < >> + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 >> + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 >> + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 >> + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 >> + >; >> + }; >> + >> pinctrl_uart2: uart2grp { >> fsl,pins = < >> MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 >> @@ -638,6 +665,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 >> >; >> }; >> >> + pinctrl_uart3: uart3grp { >> + fsl,pins = < >> + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 >> + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 >> + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 >> + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 >> + >; >> + }; >> + >> pinctrl_usdhc2: usdhc2grp { >> fsl,pins = < >> MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 >> -- >> 2.37.1 >> >> >>
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