Messages in this thread | | | From | bchihi@baylibre ... | Subject | [v2, 0/2] Fix broken SET/CLR mode of a certain number of pins for MediaTek MT8385 SoC | Date | Fri, 21 Oct 2022 10:47:06 +0200 |
| |
From: Balsam CHIHI <bchihi@baylibre.com>
On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly. To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC. This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
This is the original patch series proposed by Fabien Parent <fparent@baylibre.com>. "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
Changelog: Changes in v2 : - Rebase on top of 6.1.0-rc1-next-20221020 - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk - Add mt8365_set_clr_mode() callback
Changes in v1 : - "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
Balsam CHIHI (2): pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callback
drivers/pinctrl/mediatek/pinctrl-mt8365.c | 18 ++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 15 +++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +++++++- 3 files changed, 40 insertions(+), 1 deletion(-)
-- 2.34.1
| |