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    SubjectRe: [RFC PATCH v3 1/2] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller
    Hi Rob,

    Thank you for the review.

    On Fri, Oct 21, 2022 at 3:10 AM Rob Herring <robh@kernel.org> wrote:
    >
    > On Wed, Oct 19, 2022 at 11:02:41PM +0100, Prabhakar wrote:
    > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    > >
    > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC.
    > >
    > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
    > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch
    > > describes the L2 cache block.
    > >
    > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    > > ---
    > > .../cache/andestech,ax45mp-cache.yaml | 125 ++++++++++++++++++
    > > .../cache/andestech,ax45mp-cache.h | 38 ++++++
    > > 2 files changed, 163 insertions(+)
    > > create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
    > > create mode 100644 include/dt-bindings/cache/andestech,ax45mp-cache.h
    > >
    > > diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
    > > new file mode 100644
    > > index 000000000000..4c86a15bda5f
    > > --- /dev/null
    > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
    > > @@ -0,0 +1,125 @@
    > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
    > > +# Copyright (C) 2022 Renesas Electronics Corp.
    > > +%YAML 1.2
    > > +---
    > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
    > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
    > > +
    > > +title: Andestech AX45MP L2 Cache Controller
    > > +
    > > +maintainers:
    > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    > > +
    > > +description:
    > > + A level-2 cache (L2C) is used to improve the system performance by providing
    > > + a larger amount of cache line entries and reasonable access delays. The L2C
    > > + is shared between cores, and a non-inclusive non-exclusive policy is used.
    > > +
    > > +select:
    > > + properties:
    > > + compatible:
    > > + contains:
    > > + enum:
    > > + - andestech,ax45mp-cache
    > > +
    > > + required:
    > > + - compatible
    > > +
    > > +properties:
    > > + compatible:
    > > + items:
    > > + - const: andestech,ax45mp-cache
    > > + - const: cache
    > > +
    > > + reg:
    > > + maxItems: 1
    > > +
    > > + interrupts:
    > > + maxItems: 1
    > > +
    > > + cache-line-size:
    > > + const: 64
    > > +
    > > + cache-level:
    > > + const: 2
    > > +
    > > + cache-sets:
    > > + const: 1024
    > > +
    > > + cache-size:
    > > + enum: [131072, 262144, 524288, 1048576, 2097152]
    > > +
    > > + cache-unified: true
    > > +
    > > + next-level-cache: true
    > > +
    > > + andestech,pma-regions:
    > > + $ref: /schemas/types.yaml#/definitions/uint32-matrix
    > > + minItems: 1
    > > + maxItems: 16
    >
    > What is the inner dimension of the matrix?
    >
    > items:
    > minItems: ?
    > maxItems: ?
    >
    minItems = maxItems = 6

    i.e. the first two entries are the address, next two is the size and
    last two is the flag.
    <0x0 0x58000000 0x0 0x08000000 0x0 (AX45MP_PMACFG_ETYP_NAPOT |
    AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
    ^^ This is
    dummy and always be 0x0

    Is the above OK?

    > > + description: Optional array of memory regions to be set as non-cacheable
    > > + bufferable regions which will be setup in the PMA.
    > > +
    > > + andestech,inst-prefetch:
    > > + description: Instruction prefetch depth
    > > + $ref: /schemas/types.yaml#/definitions/uint32
    > > + enum: [ 0, 1, 2, 3 ]
    > > +
    > > + andestech,data-prefetch:
    > > + description: Data prefetch depth
    > > + $ref: /schemas/types.yaml#/definitions/uint32
    > > + enum: [ 0, 1, 2, 3 ]
    > > +
    > > + andestech,tag-ram-ctl:
    > > + description: Tag RAM output cycle. First tuple indicates output cycle and the
    > > + second tuple indicates setup cycle.
    > > + $ref: /schemas/types.yaml#/definitions/uint8-array
    > > + items:
    > > + - minimum: 0
    > > + maximum: 2
    > > + - minimum: 0
    > > + maximum: 2
    >
    > maxItems: 2
    > items:
    > maximum: 2
    >
    > 'items' without the '-' applies to all items.
    >
    > And the minimum is already 0.
    >
    Thanks for the suggestion, I'll fix it in the next version.

    > > +
    > > + andestech,data-ram-ctl:
    > > + description: Data RAM output cycle. First tuple indicates output cycle and the
    > > + second tuple indicates setup cycle.
    > > + $ref: /schemas/types.yaml#/definitions/uint8-array
    > > + items:
    > > + - minimum: 0
    > > + maximum: 2
    > > + - minimum: 0
    > > + maximum: 2
    >
    > Same here.
    >
    Ditto.

    Cheers,
    Prabhakar

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