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    Subject[PATCH 6.0 601/862] clk: ast2600: BCLK comes from EPLL
    Date
    From: Joel Stanley <joel@jms.id.au>

    [ Upstream commit b8c1dc9c00b252b3be853720a71b05ed451ddd9f ]

    This correction was made in the u-boot SDK recently. There are no
    in-tree users of this clock so the impact is minimal.

    Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
    Link: https://github.com/AspeedTech-BMC/u-boot/commit/8ad54a5ae15f27fea5e894cc2539a20d90019717
    Signed-off-by: Joel Stanley <joel@jms.id.au>
    Link: https://lore.kernel.org/r/20220421040426.171256-1-joel@jms.id.au
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/clk-ast2600.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
    index 24dab2312bc6..9c3305bcb27a 100644
    --- a/drivers/clk/clk-ast2600.c
    +++ b/drivers/clk/clk-ast2600.c
    @@ -622,7 +622,7 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
    regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */

    /* P-Bus (BCLK) clock divider */
    - hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
    + hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0,
    scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
    ast2600_div_table,
    &aspeed_g6_clk_lock);
    --
    2.35.1


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