Messages in this thread | | | From | Yu Zhao <> | Date | Tue, 18 Oct 2022 23:51:00 -0600 | Subject | Re: [PATCH v14 08/14] mm: multi-gen LRU: support page table walks |
| |
On Thu, Oct 13, 2022 at 9:04 AM Peter Zijlstra <peterz@infradead.org> wrote: > > On Mon, Aug 15, 2022 at 01:13:27AM -0600, Yu Zhao wrote: > > + for (i = pmd_index(start), addr = start; addr != end; i++, addr = next) { > > + pmd_t val = pmd_read_atomic(pmd + i); > > + > > + /* for pmd_read_atomic() */ > > + barrier(); > > Please clarify the above. This is an entirely inadequate ordering > comment.
If it's acceptable, I'll copy what we have in pmd_none_or_clear_bad_unless_trans_huge():
pmd_t pmdval = pmd_read_atomic(pmd);
/* See pmd_none_or_trans_huge_or_clear_bad for info on barrier */ #ifdef CONFIG_TRANSPARENT_HUGEPAGE barrier(); #endif
if (pmd_none(pmdval)) return 1;
pmd_read_atomic() should have a built-in READ_ONCE() in the first place. If we have to use pmd_read_atomic(), it means we are not under PMD PTL. So we can also race with pte_alloc(), regardless of THP split. In this case, compiler reordering probably won't cause any real damage, but technically not having barrier() is still a bug and will trigger KCSAN warnings, I think.
| |