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    Subject[PATCH 6.0 081/862] arm64: errata: Add Cortex-A55 to the repeat tlbi list
    Date
    From: James Morse <james.morse@arm.com>

    commit 171df58028bf4649460fb146a56a58dcb0c8f75a upstream.

    Cortex-A55 is affected by an erratum where in rare circumstances the
    CPUs may not handle a race between a break-before-make sequence on one
    CPU, and another CPU accessing the same page. This could allow a store
    to a page that has been unmapped.

    Work around this by adding the affected CPUs to the list that needs
    TLB sequences to be done twice.

    Signed-off-by: James Morse <james.morse@arm.com>
    Cc: <stable@vger.kernel.org>
    Link: https://lore.kernel.org/r/20220930131959.3082594-1-james.morse@arm.com
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    Documentation/arm64/silicon-errata.rst | 2 ++
    arch/arm64/Kconfig | 17 +++++++++++++++++
    arch/arm64/kernel/cpu_errata.c | 5 +++++
    3 files changed, 24 insertions(+)

    --- a/Documentation/arm64/silicon-errata.rst
    +++ b/Documentation/arm64/silicon-errata.rst
    @@ -76,6 +76,8 @@ stable kernels.
    +----------------+-----------------+-----------------+-----------------------------+
    | ARM | Cortex-A55 | #1530923 | ARM64_ERRATUM_1530923 |
    +----------------+-----------------+-----------------+-----------------------------+
    +| ARM | Cortex-A55 | #2441007 | ARM64_ERRATUM_2441007 |
    ++----------------+-----------------+-----------------+-----------------------------+
    | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
    +----------------+-----------------+-----------------+-----------------------------+
    | ARM | Cortex-A57 | #852523 | N/A |
    --- a/arch/arm64/Kconfig
    +++ b/arch/arm64/Kconfig
    @@ -632,6 +632,23 @@ config ARM64_ERRATUM_1530923
    config ARM64_WORKAROUND_REPEAT_TLBI
    bool

    +config ARM64_ERRATUM_2441007
    + bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
    + default y
    + select ARM64_WORKAROUND_REPEAT_TLBI
    + help
    + This option adds a workaround for ARM Cortex-A55 erratum #2441007.
    +
    + Under very rare circumstances, affected Cortex-A55 CPUs
    + may not handle a race between a break-before-make sequence on one
    + CPU, and another CPU accessing the same page. This could allow a
    + store to a page that has been unmapped.
    +
    + Work around this by adding the affected CPUs to the list that needs
    + TLB sequences to be done twice.
    +
    + If unsure, say Y.
    +
    config ARM64_ERRATUM_1286807
    bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
    default y
    --- a/arch/arm64/kernel/cpu_errata.c
    +++ b/arch/arm64/kernel/cpu_errata.c
    @@ -214,6 +214,11 @@ static const struct arm64_cpu_capabiliti
    ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
    },
    #endif
    +#ifdef CONFIG_ARM64_ERRATUM_2441007
    + {
    + ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
    + },
    +#endif
    #ifdef CONFIG_ARM64_ERRATUM_2441009
    {
    /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */

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