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    Subject[PATCH 6.0 821/862] usb: dwc3: core: Enable GUCTL1 bit 10 for fixing termination error after resume bug
    Date
    From: Piyush Mehta <piyush.mehta@amd.com>

    [ Upstream commit 63d7f9810a38102cdb8cad214fac98682081e1a7 ]

    When configured in HOST mode, after issuing U3/L2 exit controller fails
    to send proper CRC checksum in CRC5 field. Because of this behavior
    Transaction Error is generated, resulting in reset and re-enumeration of
    usb device attached. Enabling chicken bit 10 of GUCTL1 will correct this
    problem.

    When this bit is set to '1', the UTMI/ULPI opmode will be changed to
    "normal" along with HS terminations, term, and xcvr signals after EOR.
    This option is to support certain legacy UTMI/ULPI PHYs.

    Added "snps,resume-hs-terminations" quirk to resolved the above issue.

    Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
    Link: https://lore.kernel.org/r/20220920052235.194272-3-piyush.mehta@amd.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/usb/dwc3/core.c | 17 +++++++++++++++++
    drivers/usb/dwc3/core.h | 4 ++++
    2 files changed, 21 insertions(+)

    diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
    index f7f1952b2901..68d986361c49 100644
    --- a/drivers/usb/dwc3/core.c
    +++ b/drivers/usb/dwc3/core.c
    @@ -1183,6 +1183,21 @@ static int dwc3_core_init(struct dwc3 *dwc)
    dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
    }

    + /*
    + * When configured in HOST mode, after issuing U3/L2 exit controller
    + * fails to send proper CRC checksum in CRC5 feild. Because of this
    + * behaviour Transaction Error is generated, resulting in reset and
    + * re-enumeration of usb device attached. All the termsel, xcvrsel,
    + * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
    + * will correct this problem. This option is to support certain
    + * legacy ULPI PHYs.
    + */
    + if (dwc->resume_hs_terminations) {
    + reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
    + reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
    + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
    + }
    +
    if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
    reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);

    @@ -1526,6 +1541,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
    "snps,dis-del-phy-power-chg-quirk");
    dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
    "snps,dis-tx-ipgap-linecheck-quirk");
    + dwc->resume_hs_terminations = device_property_read_bool(dev,
    + "snps,resume-hs-terminations");
    dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
    "snps,parkmode-disable-ss-quirk");
    dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
    diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
    index 11975a03316f..3ac9313e66f9 100644
    --- a/drivers/usb/dwc3/core.h
    +++ b/drivers/usb/dwc3/core.h
    @@ -263,6 +263,7 @@
    #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
    #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
    #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
    +#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)

    /* Global Status Register */
    #define DWC3_GSTS_OTG_IP BIT(10)
    @@ -1097,6 +1098,8 @@ struct dwc3_scratchpad_array {
    * change quirk.
    * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
    * check during HS transmit.
    + * @resume-hs-terminations: Set if we enable quirk for fixing improper crc
    + * generation after resume from suspend.
    * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
    * instances in park mode.
    * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
    @@ -1312,6 +1315,7 @@ struct dwc3 {
    unsigned dis_u2_freeclk_exists_quirk:1;
    unsigned dis_del_phy_power_chg_quirk:1;
    unsigned dis_tx_ipgap_linecheck_quirk:1;
    + unsigned resume_hs_terminations:1;
    unsigned parkmode_disable_ss_quirk:1;
    unsigned gfladj_refclk_lpm_sel:1;

    --
    2.35.1


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