Messages in this thread | | | Date | Tue, 18 Oct 2022 16:09:27 +0800 | Subject | Re: [PATCH V2] LoongArch: Add unaligned access support | From | WANG Xuerui <> |
| |
On 2022/10/18 15:48, David Laight wrote: > From: Huacai Chen >> Sent: 18 October 2022 08:33 > ... >>> What about my more structured approach in another reply that avoids the >>> huge else-if conditions? Both the terrible line wraps and codegen could >>> be avoided. > ... >> OK, let me try. > > I suspect you can mask out some 'operand size' bits from the > instructions - instead of checking each opcode.
Technically LoongArch instruction formats don't contain any "operand size bit", because most current opcodes seem to be simply sequentially allocated. While there seem to exist a certain pattern in e.g. encodings of {LD,ST,FLD,FST}.{B,H,W,D}, I believe it's just coincidence (e.g. bits 23:22 of those instructions seem to represent "B/H/W/D"; but other instructions clearly don't follow such a pattern, not even the {LD,ST}.{BU,HU,WU} ones).
For now I'd personally prefer readability and maintainability over performance, because traps are already expensive enough that optimizations like this don't really matter.
-- WANG "xen0n" Xuerui
Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/
| |