Messages in this thread | | | Date | Wed, 19 Oct 2022 08:31:13 +0530 | Subject | Re: [PATCH V4 1/7] arm64/perf: Add BRBE registers and fields | From | Anshuman Khandual <> |
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On 10/18/22 19:26, Mark Brown wrote: > On Mon, Oct 17, 2022 at 11:27:07AM +0530, Anshuman Khandual wrote: > > I spotted one typo below but otherwise this looks good! > >> +# This is just a dummy register declaration to get all common field masks and >> +# shifts for accessing given BRBINF contents. >> +Sysreg BRBINF_EL1 2 1 8 0 0 > > This seems reasonable to me, others may disagree. > >> +Sysreg BRBCR_EL1 2 1 9 0 0 >> +Res0 63:24 >> +Field 23 EXCEPTION >> +Field 22 ERTN >> +Res0 21:9 >> +Field 8 FZP >> +Res0 7 >> +Enum 6:5 TS >> + 0b1 VIRTUAL > > I'd have expected this to be written as 0b01. Doesn't make any > practical difference though.
Sure, will change.
> >> +Sysreg BRBFCR_EL1 2 1 9 0 1 > >> +Field 16 EnL > > This is "EnI" in DDI0487I.a.
Okay, will replace "EnL" with "EnI" instead.
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