Messages in this thread | | | Date | Tue, 18 Oct 2022 20:41:47 +0200 | From | Robert Richter <> | Subject | Re: [PATCH v2 06/12] cxl/acpi: Extract component registers of restricted hosts from RCRB |
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On 18.10.22 15:31:16, Rafael J. Wysocki wrote: > On Tue, Oct 18, 2022 at 3:24 PM Robert Richter <rrichter@amd.com> wrote: > > > > A downstream port must be connected to a component register block. > > For restricted hosts the base address is determined from the RCRB. The > > RCRB is provided by the host's CEDT CHBS entry. Rework CEDT parser to > > get the RCRB and add code to extract the component register block from > > it. > > > > RCRB's BAR[0..1] point to the component block containing CXL subsystem > > component registers. MEMBAR extraction follows the PCI base spec here, > > esp. 64 bit extraction and memory range alignment (6.0, 7.5.1.2.1). > > > > Note: Right now the component register block is used for HDM decoder > > capability only which is optional for RCDs. If unsupported by the RCD, > > the HDM init will fail. It is future work to bypass it in this case. > > > > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > > What does this S-o-B mean? If this person is your co-developer, you > need to add a Co-developed-by tag to clarify that. > > > Signed-off-by: Robert Richter <rrichter@amd.com>
I picked up an early patch and modified it significantly, so I just left the S-o-B. I could change this to a Co-developed-by tag. IMO, the S-o-B is ok, but could be wrong here.
-Robert
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