Messages in this thread | | | Subject | Re: [PATCH v4 4/4] clk: mxl: Fix a clk entry by adding relevant flags | From | Stephen Boyd <> | Date | Mon, 17 Oct 2022 15:29:07 -0700 |
| |
Quoting Rahul Tanwar (2022-10-12 23:48:33) > One of the clock entry "dcl" clk has some HW limitations. One is that > its rate can only by changed by changing its parent clk's rate & two > is that HW does not support enable/disable for this clk. > > Handle above two limitations by adding relevant flags. Add standard > flag CLK_SET_RATE_PARENT to handle rate change and add driver internal > flag DIV_CLK_NO_MASK to handle enable/disable. > > Fixes: d058fd9e8984c ("clk: intel: Add CGU clock driver for a new SoC") > Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com> > Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com> > ---
Applied to clk-next
| |