Messages in this thread | | | Date | Thu, 13 Oct 2022 18:37:22 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v8 6/7] apei/ghes: Use unrcu_pointer for cmpxchg |
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On Thu, Oct 13, 2022 at 05:41:06PM +0200, Ard Biesheuvel wrote: > No it definitely does not imply that. A memory clobber is a codegen > construct, and the hardware could still complete the writes in a way > that could result in another observer seeing a mix of old and new > values that is inconsistent with the ordering of the stores as issued > by the compiler.
Yes, but look at the code. There's a:
smp_wmb();
which on x86 is
#define smp_wmb() barrier()
which is
#define barrier() __asm__ __volatile__("": : :"memory")
so there wasn't a hardware memory barrier there in the first place.
Unless ARM does something else in those primitives...
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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