Messages in this thread | | | Date | Wed, 12 Oct 2022 01:52:18 +0800 | Subject | Re: [PATCH v1 17/30] dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings | From | Hal Feng <> |
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On Fri, 30 Sep 2022 12:58:12 +0200, Krzysztof Kozlowski wrote: > On 30/09/2022 00:26, Hal Feng wrote: > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > Add bindings for the system clock generator on the JH7110 > > RISC-V SoC by StarFive Technology Ltd. > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> > > (...) > > > + '#clock-cells': > > + const: 1 > > + description: > > + See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices. > > + > > +required: > > + - compatible > > + - clocks > > + - clock-names > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + syscrg_clk: clock-controller@13020000 { > > Does not look like you tested the bindings. Please run `make > dt_binding_check` (see > Documentation/devicetree/bindings/writing-schema.rst for instructions).
Will rewrite the bindings and test them. Thanks.
Best regards, Hal
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