Messages in this thread | | | Date | Tue, 11 Oct 2022 14:47:12 +0100 | From | Jonathan Cameron <> | Subject | Re: [RFC V2 PATCH 06/11] cxl/mem: Trace DRAM Event Record |
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On Mon, 10 Oct 2022 15:41:26 -0700 ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com> > > CXL rev 3.0 section 8.2.9.2.1.2 defines the DRAM Event Record. > > Determine if the event read is a DRAM event record and if so trace the > record. > > Signed-off-by: Ira Weiny <ira.weiny@intel.com> >
Trivial comments inline
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h > index 82a8d3b750a2..7a90cfea348b 100644 > --- a/include/trace/events/cxl.h > +++ b/include/trace/events/cxl.h > @@ -230,6 +230,100 @@ TRACE_EVENT(general_media, > ) > ); >
> + > +TRACE_EVENT(dram, > + > + TP_PROTO(const char *dev_name, enum cxl_event_log_type log, > + struct cxl_event_dram *rec), > + > + TP_ARGS(dev_name, log, rec), > + > + TP_STRUCT__entry( > + CXL_EVT_TP_entry > + /* DRAM */ > + __field(u64, phys_addr) > + __field(u8, descriptor) > + __field(u8, type) > + __field(u8, transaction_type) > + __field(u8, channel) > + __field(u16, validity_flags) > + __field(u16, column) /* Out of order to pack trace record */ > + __field(u32, nibble_mask) > + __field(u32, row) > + __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) > + __array(u8, reserved, CXL_EVENT_DER_RES_SIZE)
If we are going to have this, why not put it at the end? Will that affect the packing badly?
> + __field(u8, rank) /* Out of order to pack trace record */ > + __field(u8, bank_group) /* Out of order to pack trace record */ > + __field(u8, bank) /* Out of order to pack trace record */ > + ), > + > + TP_fast_assign( > + CXL_EVT_TP_fast_assign(dev_name, log, rec->hdr); > + > + /* DRAM */ > + __entry->phys_addr = le64_to_cpu(rec->phys_addr); > + __entry->descriptor = rec->descriptor; > + __entry->type = rec->type; > + __entry->transaction_type = rec->transaction_type; > + __entry->validity_flags = get_unaligned_le16(rec->validity_flags); > + __entry->channel = rec->channel; > + __entry->rank = rec->rank; > + __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); > + __entry->bank_group = rec->bank_group; > + __entry->bank = rec->bank; > + __entry->row = get_unaligned_le24(rec->row); > + __entry->column = get_unaligned_le16(rec->column); > + memcpy(__entry->cor_mask, &rec->correction_mask, > + CXL_EVENT_DER_CORRECTION_MASK_SIZE); > + memcpy(__entry->reserved, &rec->reserved, > + CXL_EVENT_DER_RES_SIZE); > + ), > + > + CXL_EVT_TP_printk("phys_addr=%llx volatile=%s desc='%s' type='%s' " \ > + "trans_type='%s' channel=%u rank=%u nibble_mask=%x " \ > + "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ > + "valid_flags='%s' reserved=%s", > + __entry->phys_addr & CXL_GMER_PHYS_ADDR_MASK, > + (__entry->phys_addr & CXL_GMER_PHYS_ADDR_VOLATILE) ? "TRUE" : "FALSE", > + show_event_desc_flags(__entry->descriptor), > + show_mem_event_type(__entry->type), > + show_trans_type(__entry->transaction_type), > + __entry->channel, __entry->rank, __entry->nibble_mask, > + __entry->bank_group, __entry->bank, > + __entry->row, __entry->column, > + __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), > + show_dram_valid_flags(__entry->validity_flags), > + __print_hex(__entry->reserved, CXL_EVENT_DER_RES_SIZE) > + ) Probably one less tab on that trailing )?
> +); > + > #endif /* _CXL_TRACE_EVENTS_H */ > > /* This part must be outside protection */
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