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    Subject[PATCH 2/5] x86/ras: X86_FEATURE_INTEL_PPIN finally has a CPUID bit
    Date
    After nine generations of adding to model specific list of CPUS that
    support PPIN (Protected Processor Inventory Number) Intel allocated
    a CPUID bit to enumerate the MSRs.

    CPUID(EAX=7, ECX=1).EBX bit 0 enumerates presence of MSR_PPIN_CTL and
    MSR_PPIN. Add it to the "scattered" CPUID bits and add an entry to the
    ppin_cpuids[] x86_match_cpu() array to catch Intel CPUs that implement
    it.

    Signed-off-by: Tony Luck <tony.luck@intel.com>
    ---
    arch/x86/kernel/cpu/common.c | 1 +
    arch/x86/kernel/cpu/scattered.c | 1 +
    2 files changed, 2 insertions(+)

    diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
    index a1e29c0844d1..3688f70ee0a2 100644
    --- a/arch/x86/kernel/cpu/common.c
    +++ b/arch/x86/kernel/cpu/common.c
    @@ -107,6 +107,7 @@ static struct ppin_info {

    static const struct x86_cpu_id ppin_cpuids[] = {
    X86_MATCH_VENDOR_FEATURE(AMD, X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
    + X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),

    /* Legacy models without CPUID enumeration */
    X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
    diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
    index 21d1f062895a..4143b1e4c5c6 100644
    --- a/arch/x86/kernel/cpu/scattered.c
    +++ b/arch/x86/kernel/cpu/scattered.c
    @@ -26,6 +26,7 @@ struct cpuid_bit {
    static const struct cpuid_bit cpuid_bits[] = {
    { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
    { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
    + { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
    { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
    { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
    { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
    --
    2.31.1
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