Messages in this thread Patch in this message | | | From | trix@redhat ... | Subject | [PATCH] clk: visconti: fix array's data insert check | Date | Fri, 7 Jan 2022 12:49:39 -0800 |
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From: Tom Rix <trix@redhat.com>
Clang build fails with pll.c:292:20: error: address of array 'ctx->clk_data.hws' will always evaluate to 'true' if (ctx->clk_data.hws && id) ~~~~~~~~~~~~~~^~~ ~~
This check protects inserting into the clk_data.hws array. clk_data is allocated a trailing element of the ctx struct. If the ctx is ok, the ctx->clk_data.hws will be ok.
Change to checking if 'id' falls outside of the array bounds.
Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Signed-off-by: Tom Rix <trix@redhat.com> --- drivers/clk/visconti/pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/visconti/pll.c b/drivers/clk/visconti/pll.c index 3b6e88bb73d5b..7f2e1016536ab 100644 --- a/drivers/clk/visconti/pll.c +++ b/drivers/clk/visconti/pll.c @@ -289,7 +289,7 @@ static void visconti_pll_add_lookup(struct visconti_pll_provider *ctx, struct clk_hw *hw_clk, unsigned int id) { - if (ctx->clk_data.hws && id) + if (id < ctx->clk_data.num) ctx->clk_data.hws[id] = hw_clk; } -- 2.26.3
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