Messages in this thread | | | Subject | Re: [PATCH v21 7/8] arm64: dts: mt8192: add svs device information | From | AngeloGioacchino Del Regno <> | Date | Fri, 7 Jan 2022 15:33:49 +0100 |
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Il 07/01/22 10:51, Roger Lu ha scritto: > Add compitable/reg/irq/clock/efuse/reset setting in svs node.
Typo: compitable => compatible .. also, you're not only adding the svs node, but also efuse: please add that information in the commit description.
> > Signed-off-by: Roger Lu <roger.lu@mediatek.com>
This patch seems to not apply on top of the current linux-next, can you please rebase it? That would resolve issues with this series and would be picked sooner.
Apart from that...
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 39 ++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index c7c7d4e017ae..c111e26489dd 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -9,6 +9,8 @@ > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h> > +#include <dt-bindings/reset/ti-syscon.h> > + > > / { > compatible = "mediatek,mt8192"; > @@ -268,6 +270,14 @@ > compatible = "mediatek,mt8192-infracfg", "syscon"; > reg = <0 0x10001000 0 0x1000>; > #clock-cells = <1>; > + > + infracfg_rst: reset-controller { > + compatible = "mediatek,infra-reset", "ti,syscon-reset"; > + #reset-cells = <1>; > + ti,reset-bits = < > + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: svs */ > + >; > + }; > }; > > pericfg: syscon@10003000 { > @@ -362,6 +372,20 @@ > status = "disabled"; > }; > > + svs: svs@1100b000 { > + compatible = "mediatek,mt8192-svs"; > + reg = <0 0x1100b000 0 0x1000>; > + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&infracfg CLK_INFRA_THERM>; > + clock-names = "main"; > + nvmem-cells = <&svs_calibration>, > + <&lvts_e_data1>; > + nvmem-cell-names = "svs-calibration-data", > + "t-calibration-data"; > + resets = <&infracfg_rst 0>; > + reset-names = "svs_rst"; > + }; > + > spi1: spi@11010000 { > compatible = "mediatek,mt8192-spi", > "mediatek,mt6765-spi"; > @@ -479,6 +503,21 @@ > #clock-cells = <1>; > }; > > + efuse: efuse@11c10000 { > + compatible = "mediatek,efuse"; > + reg = <0 0x11c10000 0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + lvts_e_data1: data1@1c0 { > + reg = <0x1c0 0x58>; > + }; > + > + svs_calibration: calib@580 { > + reg = <0x580 0x68>; > + }; > + }; > + > i2c3: i2c3@11cb0000 { > compatible = "mediatek,mt8192-i2c"; > reg = <0 0x11cb0000 0 0x1000>, >
-- AngeloGioacchino Del Regno Software Engineer
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