Messages in this thread | | | From | Stephen Boyd <> | Date | Thu, 6 Jan 2022 16:15:39 -0800 | Subject | Re: [PATCH v3] drm/msm/dp: add support of tps4 (training pattern 4) for HBR3 |
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Quoting Kuogee Hsieh (2022-01-06 09:14:56) > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 39558a2..ba70387 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1189,12 +1190,20 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > > *training_step = DP_TRAINING_2; > > - if (drm_dp_tps3_supported(ctrl->panel->dpcd)) > + if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { > + pattern = DP_TRAINING_PATTERN_4; > + state_ctrl_bit = 4; > + } > + else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { > pattern = DP_TRAINING_PATTERN_3; > - else > + state_ctrl_bit = 3; > + } > + else {
This should be
} else {
> pattern = DP_TRAINING_PATTERN_2; > + state_ctrl_bit = 2; > + } > > - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); > + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); > if (ret) > return ret; >
With that fixed
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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