| Date | Thu, 6 Jan 2022 13:37:12 +0100 | Subject | Re: [PATCH v2 07/35] brcmfmac: pcie: Read Apple OTP information | From | Arend van Spriel <> |
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On 1/4/2022 8:26 AM, Hector Martin wrote: > On Apple platforms, the One Time Programmable ROM in the Broadcom chips > contains information about the specific board design (module, vendor, > version) that is required to select the correct NVRAM file. Parse this > OTP ROM and extract the required strings. > > Note that the user OTP offset/size is per-chip. This patch does not add > any chips yet.
Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com> > Signed-off-by: Hector Martin <marcan@marcan.st> > --- > .../broadcom/brcm80211/brcmfmac/pcie.c | 219 ++++++++++++++++++ > include/linux/bcma/bcma_driver_chipcommon.h | 1 + > 2 files changed, 220 insertions(+) > > diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c > index a52a6f8081eb..74c9a4f74813 100644 > --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c > +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
[...]
> +static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo) > +{ > + const struct pci_dev *pdev = devinfo->pdev; > + struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev); > + u32 coreid, base, words, idx, sromctl; > + u16 *otp; > + struct brcmf_core *core; > + int ret; > + > + switch (devinfo->ci->chip) { > + default: > + /* OTP not supported on this chip */ > + return 0; > + }
Does not seem this code is put to work yet. Will dive into it later on.
> + core = brcmf_chip_get_core(devinfo->ci, coreid); > + if (!core) { > + brcmf_err(bus, "No OTP core\n"); > + return -ENODEV; > + } > + > + if (coreid == BCMA_CORE_CHIPCOMMON) { > + /* Chips with OTP accessed via ChipCommon need additional > + * handling to access the OTP > + */ > + brcmf_pcie_select_core(devinfo, coreid); > + sromctl = READCC32(devinfo, sromcontrol); > + > + if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) { > + /* Chip lacks OTP, try without it... */ > + brcmf_err(bus, > + "OTP unavailable, using default firmware\n"); > + return 0; > + } > + > + /* Map OTP to shadow area */ > + WRITECC32(devinfo, sromcontrol, > + sromctl | BCMA_CC_SROM_CONTROL_OTPSEL); > + } > + > + otp = kzalloc(sizeof(u16) * words, GFP_KERNEL); > + > + /* Map bus window to SROM/OTP shadow area in core */ > + base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base);
I guess this changes the bar window...
> + brcmf_dbg(PCIE, "OTP data:\n"); > + for (idx = 0; idx < words; idx++) { > + otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx); > + brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]); > + } > + > + if (coreid == BCMA_CORE_CHIPCOMMON) { > + brcmf_pcie_select_core(devinfo, coreid);
... which is why you need to reselect the core. Otherwise it makes no sense to me.
> + WRITECC32(devinfo, sromcontrol, sromctl); > + } > + > + ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words); > + kfree(otp); > + > + return ret; > +} [unhandled content-type:application/pkcs7-signature] |